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* nir: Make boolean conversions sized just like the othersJason Ekstrand2018-12-051-4/+4
* nir: Make nir_lower_clip_vs optionally work with variables.Kenneth Graunke2018-11-191-1/+2
* v3d: Don't try to set PF flags on a LDTMU operationEric Anholt2018-11-151-0/+6
* v3d: Update the TLB config for depth writes on V3D 4.2.Eric Anholt2018-11-011-8/+22
* v3d: Use nir_remove_unused_io_vars to handle binner shader output DCEEric Anholt2018-10-302-45/+13
* v3d: Only add output slot tracking for the current varying slot.Eric Anholt2018-10-301-1/+1
* v3d: Use nir_lower_io_to_scalar_early to DCE unused VS input components.Eric Anholt2018-10-301-0/+16
* v3d: Don't rely on sorting input vars for VPM read setup.Eric Anholt2018-10-301-28/+20
* v3d: Split out NIR input setup between FS and VPM.Eric Anholt2018-10-301-47/+80
* util: use C99 declaration in the for-loop hash_table_foreach() macroEric Engestrom2018-10-252-3/+0
* v3d: Add support for hardware pack/unpack of half floats.Eric Anholt2018-10-151-0/+16
* v3d: Fix setup of the VCM cache size.Eric Anholt2018-09-071-1/+2
* v3d: Emit the VCM_CACHE_SIZE packet.Eric Anholt2018-08-062-1/+22
* v3d: Avoid spilling that breaks the r5 usage after a ldvary.Eric Anholt2018-08-061-0/+9
* v3d: Make sure that QPU instruction-has-a-dest matches VIR.Eric Anholt2018-08-062-1/+11
* v3d: Wait for TMU writes to complete before continuing after a spill.Eric Anholt2018-08-061-1/+6
* v3d: Make sure we don't emit a thrsw before the last one finished.Eric Anholt2018-08-061-2/+13
* v3d: Add some debug code for forcing register spilling.Eric Anholt2018-08-061-0/+14
* v3d: Add support for the TMUWT instruction.Eric Anholt2018-07-313-3/+13
* vc4: Fix meson build when enabled without v3d.Eric Anholt2018-07-291-0/+2
* nir: Add flipping of gl_PointCoord.y in nir_lower_wpos_ytransform.Eric Anholt2018-07-261-0/+1
* v3d: Implement a small immediates optimization, based on VC4's.Eric Anholt2018-07-237-19/+142
* v3d: Return an invalid src number if asked for a missing implicit uniform.Eric Anholt2018-07-232-3/+3
* v3d: Skip emitting texture config parameter 2 if it's just the defaults.Eric Anholt2018-07-231-1/+5
* v3d: Update an XXX comment for a path we handled in HW on V3D 4.x.Eric Anholt2018-07-231-1/+1
* v3d: Switch to using the new SFU instructions on V3D 4.x.Eric Anholt2018-07-236-24/+87
* v3d: Fix the name of the "flpop" operation.Eric Anholt2018-07-232-2/+2
* v3d: Drop unused vir_SAT() operation.Eric Anholt2018-07-231-8/+0
* v3d: Rotate through registers to improve post-RA scheduling options.Eric Anholt2018-07-231-0/+45
* v3d: Allow reading from physical regs written in the previous instruction.Eric Anholt2018-07-231-24/+0
* v3d: Disable shader-db cycle estimates until we sort out TMU estimates.Eric Anholt2018-07-161-1/+4
* v3d: Emit the lowered uniform just before its first use in a block.Eric Anholt2018-07-161-20/+18
* v3d: Add an assert that we don't provide an invalid texture return words.Eric Anholt2018-07-161-0/+8
* v3d: Apply GFXH-1625 restriction on TMUWT in the end of the shader.Eric Anholt2018-07-161-0/+4
* v3d: Implement noperspective varyings on V3D 4.x.Eric Anholt2018-07-093-3/+8
* v3d: Add support for GL_SAMPLE_ALPHA_TO_ONE.Eric Anholt2018-07-051-0/+3
* v3d: Respect swap_color_rb for the f32_color_rb case.Eric Anholt2018-07-051-5/+7
* v3d: Implement ALPHA_TO_COVERAGE.Eric Anholt2018-06-202-2/+15
* v3d: Limit shader threading according to our maximum TMU fifo usage.Eric Anholt2018-06-151-10/+24
* v3d: Fix shaders using pixel center W but no varyings.Eric Anholt2018-06-153-15/+8
* v3d: Fix configuration setup of mixed f32 and f16 render targets.Eric Anholt2018-06-141-1/+1
* v3d: Remove unused QUNIFORM_STENCIL left over from vc4.Eric Anholt2018-06-141-2/+0
* v3d: Fix undefined results for a swap_color_rb RT from a float shader output.Eric Anholt2018-06-141-1/+4
* v3d: Enable the new NIR bitfield operation lowering paths.Eric Anholt2018-06-061-2/+19
* broadcom/vc5: Add support for centroid varyings.Eric Anholt2018-04-263-0/+44
* broadcom/vc5: Add validation that we don't violate GFXH-1633 requirements.Eric Anholt2018-04-261-0/+13
* broadcom/vc5: Add validation that we don't violate GFXH-1625 requirements.Eric Anholt2018-04-261-0/+5
* broadcom/vc5: Add QPU validation for register writes after thrend.Eric Anholt2018-04-261-3/+31
* broadcom/vc5: Remove leftover vc4 MSAA lowering setup in the FS key.Eric Anholt2018-04-251-12/+5
* util: Move util_is_power_of_two to bitscan.h and rename to util_is_power_of_t...Ian Romanick2018-03-291-2/+2
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