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* v3d: Implement noperspective varyings on V3D 4.x.Eric Anholt2018-07-093-3/+8
* v3d: Add support for GL_SAMPLE_ALPHA_TO_ONE.Eric Anholt2018-07-051-0/+3
* v3d: Respect swap_color_rb for the f32_color_rb case.Eric Anholt2018-07-051-5/+7
* v3d: Implement ALPHA_TO_COVERAGE.Eric Anholt2018-06-202-2/+15
* v3d: Limit shader threading according to our maximum TMU fifo usage.Eric Anholt2018-06-151-10/+24
* v3d: Fix shaders using pixel center W but no varyings.Eric Anholt2018-06-153-15/+8
* v3d: Fix configuration setup of mixed f32 and f16 render targets.Eric Anholt2018-06-141-1/+1
* v3d: Remove unused QUNIFORM_STENCIL left over from vc4.Eric Anholt2018-06-141-2/+0
* v3d: Fix undefined results for a swap_color_rb RT from a float shader output.Eric Anholt2018-06-141-1/+4
* v3d: Enable the new NIR bitfield operation lowering paths.Eric Anholt2018-06-061-2/+19
* broadcom/vc5: Add support for centroid varyings.Eric Anholt2018-04-263-0/+44
* broadcom/vc5: Add validation that we don't violate GFXH-1633 requirements.Eric Anholt2018-04-261-0/+13
* broadcom/vc5: Add validation that we don't violate GFXH-1625 requirements.Eric Anholt2018-04-261-0/+5
* broadcom/vc5: Add QPU validation for register writes after thrend.Eric Anholt2018-04-261-3/+31
* broadcom/vc5: Remove leftover vc4 MSAA lowering setup in the FS key.Eric Anholt2018-04-251-12/+5
* util: Move util_is_power_of_two to bitscan.h and rename to util_is_power_of_t...Ian Romanick2018-03-291-2/+2
* broadcom/vc5: Start using nir_opt_move_load_ubo().Eric Anholt2018-03-281-0/+2
* broadcom/vc5: Fix extraneous register index in QIR dumping of TLBU writes.Eric Anholt2018-03-261-0/+1
* broadcom/vc5: Account for InstanceID/VertexID in VPM segment size.Eric Anholt2018-03-221-4/+9
* broadcom/vc5: Set up a vertex position if the shader doesn't.Eric Anholt2018-03-221-0/+22
* broadcom/vc5: Fix up the NIR types of FS outputs generated by NIR-to-TGSI.Eric Anholt2018-03-212-0/+38
* broadcom/vc5: Don't annotate dumps with stale live intervals.Eric Anholt2018-03-194-2/+8
* broadcom/vc5: Add support for register spilling.Eric Anholt2018-03-194-11/+276
* broadcom/vc5: Remove redundant last_inst lookup.Eric Anholt2018-03-191-1/+0
* broadcom/vc5: On QPU pack error, dump the instruction and return cleanly.Eric Anholt2018-03-191-1/+7
* broadcom/vc5: Add cursors to the compiler infrastructure, like NIR's.Eric Anholt2018-03-193-8/+73
* broadcom/vc5: Move the umul macro to a header.Eric Anholt2018-03-192-8/+8
* broadcom/vc5: Correct the arg count of TIDX/EIDX.Eric Anholt2018-03-191-2/+2
* broadcom/vc5: Re-do live variables after removing thrsws.Eric Anholt2018-03-192-3/+14
* broadcom/vc5: Extract v3d_qpu_writes_tmu() helper.Eric Anholt2018-03-191-6/+1
* nir: add lower_ldexp to nir compiler optionsTimothy Arceri2018-02-281-0/+1
* broadcom/vc5: Try to merge more than 2 QPU instructions together.Eric Anholt2018-02-051-5/+13
* broadcom/vc5: Remove no-op MOVs after register allocation.Eric Anholt2018-02-051-1/+60
* broadcom/vc5: Add missing shader-db instruction counting.Eric Anholt2018-02-051-0/+7
* broadcom/vc5: Fix a segfault on mix of booleans.Eric Anholt2018-02-011-1/+3
* nir: add lower_all_io_to_temps flagTimothy Arceri2018-01-311-0/+1
* broadcom/vc5: Update the compiler for V3D 4.2.Eric Anholt2018-01-271-2/+6
* broadcom/vc5: Use MSF to ignore discards/non-dispatched channels in loops.Eric Anholt2018-01-121-1/+5
* broadcom/vc5: Use XOR instead of SUB for execute flags comparisons.Eric Anholt2018-01-121-3/+3
* broadcom/vc5: Also check the update flags for avoiding DCE.Eric Anholt2018-01-121-1/+5
* broadcom/vc5: Add support for loading varyings in V3D 4.1.Eric Anholt2018-01-126-17/+13
* broadcom/vc5: Add compiler support for V3D 4.x texturing.Eric Anholt2018-01-126-6/+282
* broadcom/vc5: Move V3D 3.3 texturing to a separate file.Eric Anholt2018-01-124-229/+266
* broadcom/vc5: Move V3D 3.3 VPM write setup to a separate file.Eric Anholt2018-01-124-34/+81
* broadcom/vc5: Use THRSW to enable multi-threaded shaders.Eric Anholt2018-01-127-76/+279
* broadcom/vc5: Properly schedule the thread-end THRSW.Eric Anholt2018-01-122-39/+137
* broadcom/vc5: Implement GFXH-1684 workaround.Eric Anholt2018-01-124-0/+20
* broadcom/vc5: Use a physical-reg-only register class for LDVPM.Eric Anholt2018-01-122-8/+21
* broadcom/vc5: Use the new LDVPM/STVPM opcodes on V3D 4.1.Eric Anholt2018-01-125-39/+87
* broadcom/vc5: Add support for V3Dv4 signal bits.Eric Anholt2018-01-127-21/+102
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