mesa.git - Unnamed repository; edit this file 'description' to name the repository.

	Commit message (Expand)	Author	Age	Files	Lines
*	v3d: Add support for CS workgroup/invocation id intrinsics.	Eric Anholt	2019-01-14	1	-0/+1
*	v3d: Avoid spilling that breaks the r5 usage after a ldvary.	Eric Anholt	2018-08-06	1	-0/+9
*	v3d: Wait for TMU writes to complete before continuing after a spill.	Eric Anholt	2018-08-06	1	-1/+6
*	v3d: Add some debug code for forcing register spilling.	Eric Anholt	2018-08-06	1	-0/+14
*	v3d: Switch to using the new SFU instructions on V3D 4.x.	Eric Anholt	2018-07-23	1	-0/+13
*	v3d: Rotate through registers to improve post-RA scheduling options.	Eric Anholt	2018-07-23	1	-0/+45
*	broadcom/vc5: Add support for register spilling.	Eric Anholt	2018-03-19	1	-4/+240
*	broadcom/vc5: Use THRSW to enable multi-threaded shaders.	Eric Anholt	2018-01-12	1	-25/+21
*	broadcom/vc5: Use a physical-reg-only register class for LDVPM.	Eric Anholt	2018-01-12	1	-7/+19
*	broadcom/vc5: Use the new LDVPM/STVPM opcodes on V3D 4.1.	Eric Anholt	2018-01-12	1	-0/+22
*	broadcom/vc5: Add support for V3Dv4 signal bits.	Eric Anholt	2018-01-12	1	-2/+2
*	broadcom: Add VC5 NIR compiler.	Eric Anholt	2017-10-10	1	-0/+254