summaryrefslogtreecommitdiffstats
path: root/src/broadcom/compiler/vir.c
Commit message (Collapse)AuthorAgeFilesLines
* v3d: Implement ALPHA_TO_COVERAGE.Eric Anholt2018-06-201-1/+2
| | | | | | There's a convenient "FTOC" instruction for generating the coverage now, unlike vc4. This fixes dEQP-GLES3.functional.multisample.fbo_4_samples.proportionality_alpha_to_coverage
* v3d: Fix shaders using pixel center W but no varyings.Eric Anholt2018-06-151-1/+1
| | | | | | | | The docs called this field "uses both center W and centroid W", but actually it's "do you need center W even if varyings don't obviously call for it?" Fixes dEQP-GLES3.functional.shaders.builtin_variable.fragcoord_w
* broadcom/vc5: Add support for centroid varyings.Eric Anholt2018-04-261-0/+4
| | | | | | | | | It would be nice to share the flags packet emit logic with flat shade flags, but I couldn't come up with a good way while still using our pack macros. We need to refactor this to shader record setup at compile time, anyway. Fixes ext_framebuffer_multisample-interpolation * centroid-*
* broadcom/vc5: Account for InstanceID/VertexID in VPM segment size.Eric Anholt2018-03-221-4/+9
| | | | | Fixes failure in GTF-GLES3.gtf.GL3Tests.draw_instanced.draw_instanced_attrib_size
* broadcom/vc5: Fix up the NIR types of FS outputs generated by NIR-to-TGSI.Eric Anholt2018-03-211-0/+33
| | | | | | | | | | Unfortunately TGSI doesn't record the type of the FS output like GLSL does, but VC5's TLB writes depend on the output's base type. Just record the type in the key at variant compile time when we've got a TGSI input and then fix it up. Fixes KHR-GLES3.packed_pixels.pbo_rectangle.rgba32i/ui and apparently a GPU hang that breaks most tests that come after it.
* broadcom/vc5: Don't annotate dumps with stale live intervals.Eric Anholt2018-03-191-0/+3
| | | | | As you're debugging register allocation, you may have changed the intervals and not recomputed yet. Just skip the dump in that case.
* broadcom/vc5: Add support for register spilling.Eric Anholt2018-03-191-0/+8
| | | | | | | | | | | | | | | Our register spilling support is nice to have since vc4 couldn't at all, but we're still very restricted due to needing to not spill during a TMU operation, or during the last segment of the program (which would be nice to spill a value of, when there's a long-lived value being passed through with little modification from the start to the end). We could do better by emitting unspills for the last-segment values just before the last thrsw, since the last segment is probably not the maximum interference area. Fixes GTF uniform_buffer_object_arrays_of_all_valid_basic_types and 3 others.
* broadcom/vc5: Remove redundant last_inst lookup.Eric Anholt2018-03-191-1/+0
| | | | The point was to get the MOV, which the MOV_dest already returned.
* broadcom/vc5: Add cursors to the compiler infrastructure, like NIR's.Eric Anholt2018-03-191-2/+27
| | | | | This will let me do lowering late in compilation using the same instruction builder as we use in nir_to_vir.
* broadcom/vc5: Add support for loading varyings in V3D 4.1.Eric Anholt2018-01-121-1/+1
| | | | | | | The LDVARY signal now writes an arbitrary register, so I took out the magic src register file and replaced it with an instruction with LDVARY set so we have somewhere to hang a QFILE_TEMP destination for register allocation.
* broadcom/vc5: Add compiler support for V3D 4.x texturing.Eric Anholt2018-01-121-1/+4
|
* broadcom/vc5: Use THRSW to enable multi-threaded shaders.Eric Anholt2018-01-121-1/+5
| | | | | This is a major performance boost on all of V3D, but is required on V3D 4.x where shaders are always either 2- or 4-threaded.
* broadcom/vc5: Implement GFXH-1684 workaround.Eric Anholt2018-01-121-0/+1
| | | | Apparently the VPM writes need to be flushed out before we end the shader.
* broadcom/vc5: Use the new LDVPM/STVPM opcodes on V3D 4.1.Eric Anholt2018-01-121-4/+3
| | | | | | | | | | | Now, instead of a magic write register for VPM stores we have an instruction to do them (which means no packing of other ALU ops into it), with the ability to reorder the VPM stores due to the offset being baked into the instruction. VPM loads also gain the ability to be reordered by packing the row into the A argument. They also no longer write to the r3 accumulator, and instead must be stored to a physical register.
* broadcom/vc5: Add support for V3Dv4 signal bits.Eric Anholt2018-01-121-3/+11
| | | | | | | The WRTMUC replaces the implicit uniform loads in the first two texture instructions. LDVPM disappears in favor of an ALU op. LDVARY, LDTMU, LDTLB, and LDUNIF*RF now write to arbitrary registers, which required passing the devinfo through to a few more functions.
* broadcom/vc5: Emit flat shade flags for varying components > 24.Eric Anholt2018-01-031-2/+6
| | | | | | | | | | This means that with no flatshading we'll emit the single-byte ZERO_ALL_FLAT_SHADE_FLAGS, and otherwise emit a set of FLAT_SHADE_FLAGS to get all the bits we need set. There's a _SET enum in the packet we could use to possibly set entire ranges of the bitfield without using another packet, but this at least fixes the conformance failure.
* broadcom/vc5: Emit proper flatshading code for glShadeModel(GL_FLAT).Eric Anholt2018-01-031-2/+0
| | | | | | | | In updating the simulator, behavior changed slightly so that our old code wasn't getting glxgears's flatshading interpolated right. Emit flat shading code just like we would for a normal flat-shaded varying, by passing a flag in the shader key for glShadeModel(GL_FLAT) state and customizing the color inputs based on that.
* broadcom/vc5: Enable NIR txd lowering on all txd instructions.Eric Anholt2017-12-141-0/+1
| | | | | | | | Fixes almost all of piglit's arb_shader_texture_lod grad tests, except for the base -texgrad/texgradcube ones which fail on what appear to be precision problems. Reviewed-by: Ian Romanick <[email protected]>
* broadcom/vc5: Add lowering for txf_ms to a txf on a 2x2-scaled texture.Eric Anholt2017-10-301-0/+1
| | | | | | | | | The HW has no native sampler support for multisample textures, but since we only need to support txf_ms and the layout is UIF, we just need to scale up the texcoords and then add in the sample. This drops the old TEXTURE_MSAA_ADDR special uniform, since we're treating MSAA textures as textures, rather than basically texbos like VC4 had to.
* broadcom/vc5: Add PIPE_TEX_WRAP_CLAMP support for linear-filtered textures.Eric Anholt2017-10-301-0/+7
| | | | | | I already had the texture's wrapping set up to use different behavior for nearest or linear, so we just needed to saturate the coordinates in linear mode to get the "proper" blend between the edge and border values.
* nir: Get rid of nir_shader::stageJason Ekstrand2017-10-201-1/+1
| | | | | | | | It's redundant with nir_shader::info::stage. Acked-by: Timothy Arceri <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* broadcom/vc5: Fix handling of interp qualifiers on builtin color inputs.Eric Anholt2017-10-101-14/+4
| | | | | The interpolation qualifier, if specified, is supposed to take precedence over glShadeModel().
* broadcom/compiler: Set up passthrough Z when doing FS discards.Eric Anholt2017-10-101-2/+3
| | | | | | | | In order to keep early-Z from writing early in a discard shader, you need to set the "modifies Z" bit in the shader state (which the new prog_data.discards will indicate). Then, in the shader we do a TLB write to make Z passthrough happen (the QPU result is ignored, so we use a NULL source).
* broadcom: Add VC5 NIR compiler.Eric Anholt2017-10-101-0/+907
This is a pretty straightforward fork of VC4's NIR compiler to VC5. The condition codes, registers, and I/O have all changed, making the backend hard to share, though their heritage is still recognizable. v2: Move to src/broadcom/compiler to match intel's layout, rename more "vc5" to "v3d", rename QIR to VIR ("V3D IR") to avoid symbol conflicts with vc4, use new v3d_debug header, add compiler init/free functions, do texture swizzling in NIR to allow optimization.