| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | v3d: writes to magic registers aren't RF writes after THREND | Jose Maria Casanova Crespo | 2019-09-05 | 1 | -1/+3 |
| * | broadcom/vc5: Add validation that we don't violate GFXH-1633 requirements. | Eric Anholt | 2018-04-26 | 1 | -0/+13 |
| * | broadcom/vc5: Add validation that we don't violate GFXH-1625 requirements. | Eric Anholt | 2018-04-26 | 1 | -0/+5 |
| * | broadcom/vc5: Add QPU validation for register writes after thrend. | Eric Anholt | 2018-04-26 | 1 | -3/+31 |
| * | broadcom/vc5: Use THRSW to enable multi-threaded shaders. | Eric Anholt | 2018-01-12 | 1 | -0/+70 |
| * | broadcom/vc5: Add support for V3Dv4 signal bits. | Eric Anholt | 2018-01-12 | 1 | -2/+4 |
| * | broadcom: Add VC5 NIR compiler. | Eric Anholt | 2017-10-10 | 1 | -0/+208 |
 |
index : mesa.git | |
| Unnamed repository; edit this file 'description' to name the repository. |
| summaryrefslogtreecommitdiffstats |