aboutsummaryrefslogtreecommitdiffstats
path: root/src/amd
Commit message (Collapse)AuthorAgeFilesLines
* radv: switch to using radv_create_shaders()Timothy Arceri2017-10-181-85/+29
| | | | Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: add radv_create_shaders() helperBas Nieuwenhuizen2017-10-181-0/+130
| | | | | | | | | This is a combined shader creation helper than will help us to create the shaders for each stage at once. This will allow us to do some link time optimisations. Signed-off-by: Timothy Arceri <[email protected]> Acked-by: Dave Airlie <[email protected]>
* radv: add radv_hash_shaders() helperBas Nieuwenhuizen2017-10-182-0/+40
| | | | | | | | This will be used to create a hash of the combined shaders in the pipeline. Signed-off-by: Timothy Arceri <[email protected]> Acked-by: Dave Airlie <[email protected]>
* radv: Add multiple shader cache store & load functions.Bas Nieuwenhuizen2017-10-182-0/+170
| | | | | Signed-off-by: Timothy Arceri <[email protected]> Acked-by: Dave Airlie <[email protected]>
* radv: Change cache datastructures for combined pipelines.Bas Nieuwenhuizen2017-10-181-38/+64
| | | | | Signed-off-by: Timothy Arceri <[email protected]> Acked-by: Dave Airlie <[email protected]>
* radv: reorder init function callsTimothy Arceri2017-10-181-2/+2
| | | | Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* ac: clean up ac_build_indexed_load function interfacesMarek Olšák2017-10-173-36/+42
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* meson: s/radv_extensions/radv_extensions_c/ to respect var conventionEric Engestrom2017-10-171-2/+2
| | | | | Suggested-by: Dylan Baker <[email protected]> Signed-off-by: Eric Engestrom <[email protected]>
* meson: track python script dependencyEric Engestrom2017-10-171-0/+1
| | | | | | Suggested-by: Andres Gomez <[email protected]> Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Dylan Baker <[email protected]>
* meson: add missing radv_extensions.c generation for libvulkan_radeonEric Engestrom2017-10-171-1/+9
| | | | | | Fixes: 17201a2eb0b1b8538713 "radv: port to using updated anv entrypoint/extension generator." Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Andres Gomez <[email protected]>
* radv/image: bump all the offset to uint64_t.Dave Airlie2017-10-171-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | So one of the CTS tests tries to allocate a 16384x1 2048 array texture. This overflows a bunch of calculations when we want it tiled as the heights goes to 128. addrlib returns us the correct size (16GB or so), but we mangle it in the htile calcs due to the 32-bit offset fields, then userspace gives us the reduced number and we try to allocate it on a heap and things blow up. We really need to give the app back the correct size for the image so we can blow up properly in memory allocation later. This should fix hangs in dEQP-VK.pipeline.render_to_image.core.1d_array.huge.width_layers.r8g8b8a8_unorm_d32_sfloat_s8_uint since Fixes: ad3d98da9f (radv: enable tc compatible htile for d32s8 also.) Now there's an open question if we should be enabling tc-compat htile at all for shallow textures like the above. This might cause some other wierd side effects in CTS even without the tc compat so: Cc: "17.2" <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: port to using updated anv entrypoint/extension generator.Dave Airlie2017-10-177-474/+480
| | | | | | | | | | This ports radv to using the anv entrypoint/extension generator code. No differences on enabled extensions list in vulkaninfo. Acked-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: enable VK_KHX_multiview always.Dave Airlie2017-10-171-4/+4
| | | | | | | | This was in the wrong place. Fixes: ba51ad2f2 (radv: Expose VK_KHX_multiview.) Acked-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: update ia_multi_vgt when executing secondary buffersSamuel Pitoiset2017-10-161-0/+5
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: be smarter with the draw packets when executing secondary buffersSamuel Pitoiset2017-10-161-2/+10
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: always dirty some states after executing secondary buffersSamuel Pitoiset2017-10-161-6/+8
| | | | | | | The spec requires the number of buffer to be greater than 0. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: be smarter with pipelines when emitting secondary buffersSamuel Pitoiset2017-10-161-2/+17
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: do not allocate CMASK for non-MSSA images with 128 bit formatsSamuel Pitoiset2017-10-143-6/+9
| | | | | | | | This saves some useless CMASK initializations/eliminations in the Vulkan SSAO demo. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: set correct INDEX_TYPE for indexed indirect draws on GFX9Samuel Pitoiset2017-10-141-2/+8
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: add the draw count buffer to the list of buffersSamuel Pitoiset2017-10-141-0/+2
| | | | | | | | | My guess is that the GPU is going to report VM faults if vkCmdDrawIndirectCountAMD() (and friends) are used. Cc: [email protected] Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: take unsafe_math and sisched into account when hashing shaders.Dave Airlie2017-10-123-9/+24
| | | | | | | | | We want to generate different variants for sisched and unsafe_math shader variants, so add them to the hash key. Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Timothy Arceri <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* ac: add radeon_info::has_sync_filecros-mesa-17.2.3-vanillachadv/cros-mesa-17.2.3-vanillaMarek Olšák2017-10-122-0/+2
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* ac/surface: add ac_surface::is_displayableMarek Olšák2017-10-122-0/+13
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* amd/addrlib: add Addr2IsValidDisplaySwizzleModeMarek Olšák2017-10-124-2/+58
| | | | | | | | Some "standard" (_S) swizzle modes are displayable on Raven, even though the micro tile mode says it's not displayable. Expose the addrlib function to the driver. Reviewed-by: Nicolai Hähnle <[email protected]>
* radv: don't crash if cache is disabled.Dave Airlie2017-10-121-5/+9
| | | | | | | | If you set MESA_GLSL_CACHE_DISABLE, radv crashed. Fixes: fd24be134f (radv: make use of on-disk cache) Signed-off-by: Dave Airlie <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* radv: use CLEAR_STATE for initializing some registersSamuel Pitoiset2017-10-121-41/+58
| | | | | | | | | Based on RadeonSI. This improves some Vulkan demos by +1% to +3%. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: add has_clear_state and enable it on CIK+ onlySamuel Pitoiset2017-10-122-1/+6
| | | | | | | | This will allow us to emit the CLEAR_STATE packet instead of a bunch of useless packets when doing CS initialization. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: do not set registers for merged ES-GS on GFX9Samuel Pitoiset2017-10-121-2/+5
| | | | | | | Based on RadeonSI. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: move the raster config emission in si_set_raster_config()Samuel Pitoiset2017-10-121-53/+60
| | | | | | | Similar to RadeonSI, also only call this function for <= VI. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: remove duplicate line of codeTimothy Arceri2017-10-121-1/+0
| | | | | | | The same line of code is a few lines above. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* radv: make use of on-disk cacheTimothy Arceri2017-10-121-2/+25
| | | | | | | | If the app provided in-memory pipeline cache doesn't yet contain what we are looking for, or it doesn't provide one at all then we fallback to the on-disk cache. Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: create on-disk shader cacheTimothy Arceri2017-10-122-0/+19
| | | | | | | This is the drivers on-disk cache intended to be used as a fallback as opposed to the pipeline cache provided by apps. Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: remove duplicate debug_flags fieldTimothy Arceri2017-10-129-17/+14
| | | | | Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: Only set the MTYPE flags on GFX9+.Bas Nieuwenhuizen2017-10-111-1/+1
| | | | | | | | Older kernels fail the va_op with this flag set. If the kernel supports GFX9 usefully, it will also support this flag. Fixes: e8d57802fea "radv/gfx9: allocate events from uncached VA space" Reviewed-by: Dave Airlie <[email protected]>
* radv: lower ffma in nir.Dave Airlie2017-10-111-0/+1
| | | | | | | | | | | | | | | | | So it appears the Vulkan SPIR-V fma opcode can be equivalent to a mad operation, and the fma hw opcode on AMD hw is issued like a double opcode so is slower. Also the radeonsi stack does this. This appears to improve performance on a number of games from Feral, and thanks to Feral for noticing the problem. I'm reposting this one as Marek indicated he thinks this is what we should be doing on AMD hw. Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Cc: "17.2" <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: Add R16G16B16A16_SNORM fast clear supportAlex Smith2017-10-111-0/+6
| | | | | | Signed-off-by: Alex Smith <[email protected]> Cc: "17.2" <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: export KHR_relaxed_block_layoutDave Airlie2017-10-101-0/+4
| | | | | | | | This seems to pass all the cts tests it enables. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Acked-by: Jason Ekstrand <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* amd: move r600d_common.h into r600gMarek Olšák2017-10-099-163/+23
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: shrink r600d_common.h and stop using itMarek Olšák2017-10-095-185/+37
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radv: configure VGT_VERTEX_REUSE at pipeline creationSamuel Pitoiset2017-10-093-10/+16
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: do not need to zero-init ds/raster statesSamuel Pitoiset2017-10-091-3/+0
| | | | | | | Already done when creating the pipeline. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: remove unused fields in radv_raster_stateSamuel Pitoiset2017-10-091-3/+0
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: set ALPHA_TO_MASK_ENABLE at blend state initSamuel Pitoiset2017-10-091-7/+7
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: emit PA_SU_POINT_{SIZE,MINMAX} in si_emit_config()Samuel Pitoiset2017-10-092-16/+15
| | | | | | | | | These registers don't change during the lifetime of the command buffer, there is no need to re-emit them when binding a new pipeline. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: allow launching waves out-of-order for computeSamuel Pitoiset2017-10-091-1/+9
| | | | | | | | Ported from RadeonSI, and -pro seems to enable it as well. Signed-off-by: Samuel Pitoiset <[email protected]> Acked-by: Nicolai Hähnle <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: convert all COMPUTE operations to the RADV_META_SAVE_XXX flagsSamuel Pitoiset2017-10-067-107/+62
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: add RADV_META_SAVE_COMPUTE_PIPELINE flagSamuel Pitoiset2017-10-062-2/+23
| | | | | | | This will allow use to merge the compute save/restore helpers. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: add radv_meta_save() helperSamuel Pitoiset2017-10-069-73/+58
| | | | | | | | And merge radv_meta_save_novertex() with radv_meta_save_graphics_reset_vport_scissor_novertex(). Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: merge radv_meta_{save,restore}_pass() with RADV_META_SAVE_PASSSamuel Pitoiset2017-10-064-39/+22
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: convert all GFX operations to the RADV_META_SAVE_XXX flagsSamuel Pitoiset2017-10-067-13/+46
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-03 20:34:56 +0000