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* radv: Implement binning on GFX9.Bas Nieuwenhuizen2017-12-314-6/+348
| | | | | | | | | | | | Overall it does not really help or hurt. The deferred demo gets 1% improvement and some games a 3% decrease, so I don't think this should be enabled by default. But with the code upstream it is easier to experiment with it. v2: Remove initializing the registers from si_emit_config. Reviewed-by: Dave Airlie <[email protected]>
* radv: Add flag for enabling binning.Bas Nieuwenhuizen2017-12-312-0/+9
| | | | | | Letting it be disabled by default. Reviewed-by: Dave Airlie <[email protected]>
* radv: Also set DCC params for sampling for input attachment usage.Bas Nieuwenhuizen2017-12-291-1/+2
| | | | | | | | Those are implemented as texture sampling, so we need to make the texture TC-compatible too. Fixes: 34d23e82ca9 "radv: set some dcc parameters depending on if texture will be sampled" Reviewed-by: Fredrik Höglund <[email protected]>
* radv: Enable DCC with transfers.Bas Nieuwenhuizen2017-12-291-2/+1
| | | | | | | | | Before this DCC was in practice disabled for most games. This enables practical DCC use. Expect a 5-10% perf increase on a bunch of games on vega @ 4k. Reviewed-by: Dave Airlie <[email protected]> Tested-by: Dieter Nützel <[email protected]>
* radv: Decompress copy destination if formats are incompatible.Bas Nieuwenhuizen2017-12-291-2/+25
| | | | | | | | | | If both source and destination are DCC compressed, and their formats are not compatible, we need to decompress one of them to make sure we can do reinterpretation (which needs src format == dst format) . Reviewed-by: Dave Airlie <[email protected]> Tested-by: Dieter Nützel <[email protected]>
* radv: Disable DCC for GENERAL layout and compute transfer dest.Bas Nieuwenhuizen2017-12-294-8/+47
| | | | | | | | | | | | | | | Apps can use this for render feedback loops, where things are defined if they render each pixel only once. However, DCC fails here, as the level of coherence is a block not a pixel, so disable it. This is also going to help implementing other stuff. Even if we optimize this later to only happen if there actually is a loop (if possible at all ...), then the machinery is still useful to exclude images accessible by the SDMA queue when that is implemented. Reviewed-by: Dave Airlie <[email protected]> Tested-by: Dieter Nützel <[email protected]>
* radv: Don't init DCC metadata during FS resolve.Bas Nieuwenhuizen2017-12-291-5/+0
| | | | | | | | It should already be valid there + the RB will update it during rendering. Reviewed-by: Dave Airlie <[email protected]> Tested-by: Dieter Nützel <[email protected]>
* radv: Make color meta operations layout aware.Bas Nieuwenhuizen2017-12-295-110/+145
| | | | | | | | | | | | | For fast clear eliminate and decompressions, we always use the most compressed format. For clears, the code already creates a renderpass on demand with the exact same layout as specified. Otherwise we start distinguishing between GENERAL and TRANSFER_DST_OPTIMAL. Reviewed-by: Dave Airlie <[email protected]> Tested-by: Dieter Nützel <[email protected]>
* radv: Add compute DCC decompress.Bas Nieuwenhuizen2017-12-293-0/+275
| | | | | | | | | | | We do an in place copy where we read compressed and write decompressed. By doing this in sizes that cover entire DCC blocks and waiting for all reads in the block before starting to write we avoid corruption. In the end we clear the DCC metadata to 0xffffffff. Reviewed-by: Dave Airlie <[email protected]> Tested-by: Dieter Nützel <[email protected]>
* radv: Use the meta fast clear destructor on construction failure.Bas Nieuwenhuizen2017-12-291-6/+3
| | | | | | | | Simplifies failure paths. The caller already calls radv_device_finish_meta_fast_clear_flush_state on failure. Reviewed-by: Dave Airlie <[email protected]> Tested-by: Dieter Nützel <[email protected]>
* radv: Add GFX DCC decompress.Bas Nieuwenhuizen2017-12-292-12/+83
| | | | | Reviewed-by: Dave Airlie <[email protected]> Tested-by: Dieter Nützel <[email protected]>
* radv: Don't enable DCC / TC compat HTILE for storage images.Bas Nieuwenhuizen2017-12-291-5/+6
| | | | | | | | | | | We don't get a layout when binding to a descriptor set, but can assume that the LAYOUT is GENERAL. For DCC stores with the DCC bits set will result in a hang, so better be safe than sorry. Reviewed-by: Dave Airlie <[email protected]> Tested-by: Dieter Nützel <[email protected]>
* Revert "radv/gfx9: fix block compression texture views."Bas Nieuwenhuizen2017-12-291-35/+0
| | | | | | | | | This reverts commit 59515780433837ad3975f8ed20b93cf2fe6870e5. The mentioned commit causes a hang in DoW3 on Vega. Fixes: 59515780433 "radv/gfx9: fix block compression texture views." Acked-by: Dave Airlie <[email protected]>
* radv/gfx9: use correct swizzle parameter to work out border swizzle.Dave Airlie2017-12-291-2/+2
| | | | | | | | | | This should fix: dEQP-VK.pipeline.sampler.view_type.*.format.b4g4r4a4_unorm_pack16.address_modes.all_mode_clamp_to_border_opaque_black and a few others in that area. Fixes: b11c4a5546 (radv: add texture descriptor/fmask/cmask support for GFX9) Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv/gfx9: use a bigger hammer to flush cb/db caches.Dave Airlie2017-12-291-1/+8
| | | | | | | | | | | | amdvlk is probably more subtle than this but it never uses the inv cb/db variants, we fail some CTS tests without this. Fixes: dEQP-VK.renderpass.dedicated_allocation.formats.d32_sfloat_s8_uint.input*. Fixes: c2fbeb7ca05 (radv: add GFX9 cache flushing support.) Reviewed-by: Bas Nieuwenhuizen <[email protected]> (for now :-) Signed-off-by: Dave Airlie <[email protected]>
* radv/gfx9: fix block compression texture views.Dave Airlie2017-12-291-0/+35
| | | | | | | | | | | | This ports a fix from amdvlk, to fix the sizing for mip levels when block compressed images are viewed using uncompressed views. Fixes: dEQP-VK.image.texel_view_compatible.graphic.extended*bc* Fixes: e38685cc62e 'Revert "radv: disable support for VEGA for now."' Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv/gfx9: fix buffer to image for 3d images on compute queuesDave Airlie2017-12-292-15/+48
| | | | | | | | | This fixes some of the broken: dEQP-VK.synchronization.op.multi_queue.*64x64x8* tests. Fixes: e38685cc62e 'Revert "radv: disable support for VEGA for now."' Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv/gfx9: fix 3d image clears on compute queuesDave Airlie2017-12-292-9/+65
| | | | | | | | | This fixes some of the broken: dEQP-VK.synchronization.op.multi_queue.*64x64x8* tests. Fixes: e38685cc62e 'Revert "radv: disable support for VEGA for now."' Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv/gfx9: fix 3d image to image transfers on compute queues.Dave Airlie2017-12-292-20/+56
| | | | | | | | | This fixes some of the broken: dEQP-VK.synchronization.op.multi_queue.*64x64x8* tests. Fixes: e38685cc62e 'Revert "radv: disable support for VEGA for now."' Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: fix pipeline statistics end query on compute queueDave Airlie2017-12-281-1/+1
| | | | | | | | | | | | It's legal to a pipeline stat query on a compute queue, but we'd emit the wrong packet here. This should fix it to emit the correct packet. Noticed while inspecting the mpv hang. Fixes: ad61eac250 (radv: factor out eop event writing code. (v2)) Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: fix events on compute queues.Dave Airlie2017-12-281-1/+1
| | | | | | | | | | | The event emission wasn't sending the correct packet for gfx8 compute queues, which explains why it works on vega fine. This fixes the mpv vulkan hang. Fixes: ad61eac250 (radv: factor out eop event writing code. (v2)) Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: move local bos usage to a perftest flag.Dave Airlie2017-12-285-1/+5
| | | | | | | | | | These seem mildly unstable on vega, crashing CTS in various fun ways, and looks like leaking memory. Disable for now, but leave the option to enable them. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: Always use fragment resolve if dest uses DCC.Bas Nieuwenhuizen2017-12-281-5/+4
| | | | | | | HW resolve does not support it either. Fixes: 2a04f5481df "radv/meta: select resolve paths" Reviewed-by: Dave Airlie <[email protected]>
* radv: Use correct framebuffer size for partial FS resolves.Bas Nieuwenhuizen2017-12-281-2/+2
| | | | | | | Framebuffer is from 0,0, not (dst.x, dst.y). Fixes: 69136f4e633 "radv/meta: add resolve pass using fragment/vertex shaders" Reviewed-by: Dave Airlie <[email protected]>
* radv: Fix fragment resolve destination offset.Bas Nieuwenhuizen2017-12-281-2/+2
| | | | | | | | | | The position start at (dst.x, dst.y), so if we want the source to start at (src.x, src.y), we have to offset by (src.x-dst.x,src.y-dst.y). Haven't tested that this fixed anything yet, but found by inspection. Fixes: 69136f4e633 "radv/meta: add resolve pass using fragment/vertex shaders" Reviewed-by: Dave Airlie <[email protected]>
* radv: Don't handle DCC in compute resolve.Bas Nieuwenhuizen2017-12-281-4/+1
| | | | | | If the destination has DCC, we will use the FS resolve. Reviewed-by: Dave Airlie <[email protected]>
* radv: Flush caches before subpass resolve.Bas Nieuwenhuizen2017-12-282-0/+18
| | | | | Fixes: f4e499ec791 "radv: add initial non-conformant radv vulkan driver" Reviewed-by: Dave Airlie <[email protected]>
* radv: Invert condition for all samples identical during resolve.Bas Nieuwenhuizen2017-12-281-1/+1
| | | | | | | | the samples_identical instruction returns 0 if they are differet, so we have to do the extra work if the result is 0, not if it is != 0. Fixes: f4e499ec791 "radv: add initial non-conformant radv vulkan driver" Reviewed-by: Dave Airlie <[email protected]>
* radv: don't do format replacement on tc compat htile surfaces.Dave Airlie2017-12-281-1/+2
| | | | | | | | | | | | For copies the texture unit needs to know the depth format so it can read the htile data properly. This fixes: dEQP-VK.renderpass.suballocation.formats.d32_sfloat_s8_uint.load.clear Fixes: ad3d98da9f (radv: enable tc compatible htile for d32s8 also.) Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv/gfx9: use correct stencil format for tc compat htile.Dave Airlie2017-12-281-4/+7
| | | | | | | | | | | This needs to correspond to the bit depth of the Z plane. noticed in passing reading amdvlk. Fixes: fc6c77e162df3 (radv: fix TC-compat HTILE with VK_FORMAT_D32_SFLOAT_S8_UINT on Vega) Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* amd/common: rework set_userdata_location() and rename to set_loc()Samuel Pitoiset2017-12-271-8/+11
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* amd/common: rename set_userdata_location_shader() to set_loc_shader()Samuel Pitoiset2017-12-271-27/+30
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* amd/common: replace set_userdata_location_indirect() by set_loc_desc()Samuel Pitoiset2017-12-271-11/+12
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* amd/common: rename radv_define_vs_user_sgprs_phase2()Samuel Pitoiset2017-12-271-22/+33
| | | | | | | ... to set_vs_specific_input_locs(). Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* amd/common: rename radv_define_common_user_sgprs_phase2()Samuel Pitoiset2017-12-271-43/+50
| | | | | | | ... to set_global_input_locs(). Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* amd/common: rename add_user_sgpr_array_argument() to add_array_arg()Samuel Pitoiset2017-12-271-9/+5
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* amd/common: replace add_sgpr_argument() by add_arg()Samuel Pitoiset2017-12-271-45/+33
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* amd/common: replace add_user_sgpr_argument() by add_arg()Samuel Pitoiset2017-12-271-45/+58
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* amd/common: replace add_vgpr_argument() by add_arg()Samuel Pitoiset2017-12-271-51/+60
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* amd/common: add new add_arg() helper for SGPRs/VGPRs argumentsSamuel Pitoiset2017-12-271-0/+24
| | | | | | | The idea is to clean up the add arguments logic. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* amd/common: rename radv_define_common_user_sgprs_phase1()Samuel Pitoiset2017-12-271-38/+74
| | | | | | | ... to declare_global_input_sgprs(). Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* amd/common: rename radv_define_vs_user_sgprs_phase1()Samuel Pitoiset2017-12-271-21/+42
| | | | | | | ... to declare_vs_specific_inputs_sgprs(). Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* amd/common: do not try to declare input VS SGPRs for GSSamuel Pitoiset2017-12-271-1/+0
| | | | | | | It's a no-op anyway but it looked strange to me, remove it. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* amd/common: add declare_vs_input_vgprs() helperSamuel Pitoiset2017-12-271-14/+16
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* amd/common: add declare_tes_input_vgprs() helperSamuel Pitoiset2017-12-271-8/+10
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* amd/common: remove unnecessary num_user_sgprs_usedSamuel Pitoiset2017-12-271-2/+0
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* amd/common: remove unnecessary user_sgpr_countSamuel Pitoiset2017-12-271-2/+0
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: set some dcc parameters depending on if texture will be sampledDave Airlie2017-12-271-1/+10
| | | | | | | | | | This is ported from amdvlk which sets the independent 64b blocks only for image which will sample dcc. I'm not sure how to port this to radeonsi. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv/radeonsi: set dcc min uncompressed properly for APUs.Dave Airlie2017-12-271-0/+10
| | | | | | | This is ported from amdvlk. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* amd/common/radv/radeonsi: use register defines for dcc block sizes.Dave Airlie2017-12-272-3/+9
| | | | | | | | These are just taken from amdvlk, we probably knew these already, but may as well port them now. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
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