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* ac/debug: Dump indirect buffers.Bas Nieuwenhuizen2017-01-094-6/+31
| | | | | | | | | | | | | | This is for handling chained command buffers and secondary command buffers. It doesn't handle the trace id for secondary command buffers yet, but I don't think that is possible in general with just writes, as we could call a secondary command buffer multiple times. I think this is good enough for now, as the most useful case is the chaining when we grow an IB. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: Dump command buffer on hang.Bas Nieuwenhuizen2017-01-096-9/+150
| | | | | | | | | | | | | v2: - Now use the filename specified by RADV_TRACE_FILE env var. - Use the same var to enable tracing. I thought we could as well always set the filename explicitly instead of having some arbitrary defaults, and at that point we don't need a separate feature enable. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* ac/debug: Move IB decode to common code.Bas Nieuwenhuizen2017-01-094-0/+405
| | | | | | Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* ac/debug: Move sid_tables.h generation to common code.Bas Nieuwenhuizen2017-01-094-2/+306
| | | | | | Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* spirv: add support for doubles to OpSpecConstantSamuel Iglesias Gonsálvez2017-01-091-1/+4
| | | | | | | | | v2 (Jason): - Fix indent in radv change - Add vtn_u64_literal() helper to take 64 bits (Jason) Signed-off-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* radv: drop unused fields in physical device.Dave Airlie2017-01-091-6/+0
| | | | Signed-off-by: Dave Airlie <[email protected]>
* radv: fix depth transitions with layerCount = VK_REMAINING_ARRAY_LAYERSPierre-Loup A. Griffais2017-01-071-1/+1
| | | | | | | | | Interpreting layerCount literally would try to create billions of image views in radv_process_depth_image_inplace(). Signed-off-by: Pierre-Loup A. Griffais <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radeonsi: do all math in bytes in SI DMA codeMarek Olšák2017-01-051-2/+4
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* anv,radv: disable StorageImageWriteWithoutFormat for nowIlia Mirkin2016-12-311-1/+1
| | | | | | | | | | | The SPIR-V capability isn't even marked as enabled, and there are no tests in Vulkan-CTS. Per Jason Ekstrand, this won't work in anv as such write-only surfaces require additional setup which is currently not performed. Signed-off-by: Ilia Mirkin <[email protected]> Acked-by: Dave Airlie <[email protected]> Acked-by: Jason Ekstrand <[email protected]>
* spirv: always expose SpvCapabilityStorageImageExtendedFormatsIlia Mirkin2016-12-291-1/+0
| | | | | | | | | | I forgot to do this in commit 76b97d544e ("anv: enable storage image extended formats"). Since both drivers support this now, no need for the conditional enable. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: only allow cmask/dcc in color optimal.Dave Airlie2016-12-301-3/+2
| | | | | | | | I had this on transfers due to the clear color cmd, but it seems like that path shouldn't get fast clears. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: only allow cmask/dcc on exclusive or concurrent with graphics queue.Dave Airlie2016-12-301-3/+6
| | | | | | | Otherwise we don't get the barriers to flush dcc etc. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: denote support for extended storage image formats.Dave Airlie2016-12-281-2/+4
| | | | | | | | | I'm sure anv has support for these as well, but this is just a first use of the interface to allow different supported spir-v features. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: add some asserts for operations on general queueDave Airlie2016-12-272-0/+3
| | | | | | These might be useful in the future, or not. Signed-off-by: Dave Airlie <[email protected]>
* radv: Also skip DCC clear flushes for compute.Bas Nieuwenhuizen2016-12-274-12/+16
| | | | | | (airlied: fixes DOOM hang with compute queue enabled) Reviewed-by: Dave Airlie <[email protected]> Signed-off-by: Bas Nieuwenhuizen <[email protected]>
* radv: handle queue present directly to winsysDave Airlie2016-12-261-1/+9
| | | | | | | | | | Don't call the QueueSubmit interface, just call direct to the winsys, so we can pass the wait semaphores. Noticed while debugging doom, doesn't fix anything. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: fix rendering to b10g11r11_ufloat_pack32Dave Airlie2016-12-261-1/+1
| | | | | | | | | | doom was causing a printf about an illegal color, it was due the non-void returning -1, and the other function checking for 4, align these. Reviewed-by: Edward O'Callaghan <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: handle multi-component shared load/stores.Dave Airlie2016-12-261-12/+29
| | | | | | | This was seen in doom shaders, so handle it properly. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave AIrlie <[email protected]>
* radv: return count of queue families writtenDamien Grassart2016-12-251-1/+4
| | | | | | | | | | The Vulkan spec indicates that vkGetPhysicalDeviceQueueFamilyProperties() should overwrite pQueueFamilyPropertyCount with the number of structures actually written to pQueueFamilyProperties. Signed-off-by: Damien Grassart <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: set some proper values for interp offset limits.Dave Airlie2016-12-231-3/+3
| | | | | | | | These are taken from the amdgpu-pro driver, and cause no CTS change. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: bump texel offsets to align with radeonsiDave Airlie2016-12-231-4/+4
| | | | | | | | | | it appears from the amdgpu-pro results the hw can do more, but let's just align with radeonsi for now. No CTS regressions. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: fix dual source blendingFredrik Höglund2016-12-221-2/+2
| | | | | | | | | | | | | | | | | | | | Add the index to the location when assigning driver locations for output variables. Otherwise two fragment shader outputs declared as: layout (location = 0, index = 0) out vec4 output1; layout (location = 0, index = 1) out vec4 output2; will end up aliasing one another. Note that this patch will make the second output variable in the above example alias a possible third output variable with location = 1 and index = 0. But this shouldn't be a problem in practice since only one color attachment is supported when dual-source blending is used. Cc: "13.0" <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: enable shaderStorageImageExtendedFormatsDave Airlie2016-12-221-1/+1
| | | | | | | This passes all the CTS tests that get enabled for this. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: enable shaderGatherImageExtendedDave Airlie2016-12-221-1/+1
| | | | | | | | | Thanks to Ilia's patch this works fine on radv. No regressions in CTS, all enabled tests pass. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv/image: only touch queue family info for concurrent images.Dave Airlie2016-12-211-2/+4
| | | | | | | | | | The spec says to ignore these fields for exclusive images. Fixes crashes in: dEQP-VK.clipping.* Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: flush smem for uniform buffer bit.Dave Airlie2016-12-211-1/+3
| | | | | | | | (cc'ing stable as I'd like to backport the ubo speedup as well) Reviewed-by: Bas Nieuwenhuizen <[email protected]> Cc: "13.0" <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radeonsi: add Polaris12 support (v3)Junwei Zhang2016-12-214-1/+8
| | | | | | | | | | | v2: use gfxip names for llvm 4.0+ v3: use tonga for llvm <= 3.8, drop gfxip name, we can just change that we change the other asics. Reviewed-by: Marek Olšák <[email protected]> Signed-off-by: Junwei Zhang <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]> Acked-by: Christian König <[email protected]>
* radv: Use correct workgroup size limits.Bas Nieuwenhuizen2016-12-181-4/+4
| | | | | | | Not sure where the 16k comes from, but pretty sure 2k is the max. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: expose the compute queueDave Airlie2016-12-181-11/+41
| | | | | | | v2: Don't expose the SDMA queue and use the CIK check also in the second if. (Bas) Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: Only emit PFP ME syncs for DMA on the GFX queue.Bas Nieuwenhuizen2016-12-181-2/+2
| | | | | Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: Create an empty CS per ring type.Bas Nieuwenhuizen2016-12-182-7/+20
| | | | | Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: Don't enable CMASK on compute queues.Bas Nieuwenhuizen2016-12-184-8/+62
| | | | | | | We can't fast clear on compute queues. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: Use RELEASE_MEM packet for MEC timestamp query.Bas Nieuwenhuizen2016-12-182-9/+21
| | | | | Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: Implement indirect dispatch for the MEC.Bas Nieuwenhuizen2016-12-181-9/+17
| | | | | Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: update vkCmdUpdateBuffer for the MEC.Bas Nieuwenhuizen2016-12-181-1/+3
| | | | | Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: Implement cache flushing for the MEC.Bas Nieuwenhuizen2016-12-181-7/+29
| | | | | Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: add semaphore supportDave Airlie2016-12-183-11/+72
| | | | Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: pass queue index into winsys submissionDave Airlie2016-12-183-5/+13
| | | | | | This is so we can submit on separate queues if needed Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: init compute queue and avoid initing transfer queuesDave Airlie2016-12-183-15/+35
| | | | Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv/winsys: Make WaitIdle queue aware.Bas Nieuwenhuizen2016-12-185-21/+38
| | | | | Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv/meta: update header infoDave Airlie2016-12-181-1/+2
| | | | Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: hook compute clears into clear image api.Dave Airlie2016-12-181-8/+33
| | | | | | | | These aren't used yet but we will want to use them when we implement a separate compute queue. Signed-off-by: Dave Airlie <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: clear image implementation for compute queueDave Airlie2016-12-183-9/+272
| | | | Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv/meta: split clear image out into a separate layer clear functionDave Airlie2016-12-181-117/+128
| | | | | | This will make it easier to add support for clears on compute queues. Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: implement image->image copies using compute shaderDave Airlie2016-12-184-6/+343
| | | | | | | | | | This is required for having a separate compute queue, we probably can't use this on GFX queue due to DCC. v2: Set coord_components = 2 for itoi texture fetch. (Bas) Signed-off-by: Dave Airlie <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: add a compute shader implementation for buffer to imageDave Airlie2016-12-183-6/+325
| | | | | | | | | | | This implements the reverse of the current buffer->image path and can be used when we need to do image transfer on compute queues This just adds the code turned off as we don't support separate computes queues yet, and we don't want to use this path on the GFX queues for DCC reasons. Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: Use correct pitch for views with different block size.Bas Nieuwenhuizen2016-12-181-1/+4
| | | | | | | | | Needed when accessing a comrpessed texture as R32G32B32A32 from a shader. This was not encountered previously, as we used the CB for the reinterpretation, which does not use this pitch. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: Store queue family in command buffers.Dave Airlie2016-12-182-2/+35
| | | | | | v2: Added helper (Bas) Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: start fixing up queue allocate for multiple queuesDave Airlie2016-12-182-15/+53
| | | | | | v2: Fix error handling and zero init the device (Bas) Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv/winsys: start adding support for DMA/compute queueDave Airlie2016-12-181-5/+20
| | | | Reviewed-by: Bas Nieuwenhuizen <[email protected]>
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