| Commit message (Collapse) | Author | Age | Files | Lines |
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It happens that some games try to access a vertex buffer without
a valid format. This case was incorrectly handled by
ac_get_tbuffer_format which made ACO emit an invalid instruction.
Signed-off-by: Timur Kristóf <[email protected]>
Cc: 19.3 <[email protected]>
Reviewed-by: Samuel Pitoiset <[email protected]>
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No pipeline-db changes.
v2: use early-exit for VOP3
Reviewed-by: Daniel Schürmann <[email protected]> (v1)
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In particular, increase the cost of 64-bit integer division.
Fixes huge shaders with dEQP-VK.spirv_assembly.type.scalar.i64.mod_geom
, with ACO used for GS this creates shaders requiring a branch with
>32767 dword offset.
Signed-off-by: Rhys Perry <[email protected]>
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
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The primitive indices have to be swapped to follow the drawing
order.
This fixes corruption with Overwatch when NGG GS is force enabled.
Signed-off-by: Samuel Pitoiset <[email protected]>
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
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The workaround got accidentally moved to the wrong place
Fixes: 08d510010b7586387e363460b98e6a45bbe97164 aco: increase accuracy of SGPR limits
Reviewed-by: Samuel Pitoiset <[email protected]>
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This extension allows to control the subgroup size by allowing a
varying subgroup size and also specifying a required subgroup size.
This implementation only allows to specify a required subgroup
size for compute shaders because there is some caveats with
other shader stages (eg. NGG with geometry shader). This
basically allows apps to use Wave32 for compute shaders.
This extension is enabled for all chips but only GFX10 supports
Wave32. ACO doesn't support it.
Signed-off-by: Samuel Pitoiset <[email protected]>
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
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Signed-off-by: Samuel Pitoiset <[email protected]>
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
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Signed-off-by: Samuel Pitoiset <[email protected]>
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
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It's always 64.
Signed-off-by: Samuel Pitoiset <[email protected]>
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
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This will allow to change wavesize on-demand.
Signed-off-by: Samuel Pitoiset <[email protected]>
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
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Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2031
Signed-off-by: Samuel Pitoiset <[email protected]>
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
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Now that all environment variables are documented, it would be
appreciated if we can keep this up-to-date.
[skip ci]
Signed-off-by: Samuel Pitoiset <[email protected]>
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
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Signed-off-by: Eric Engestrom <[email protected]>
Reviwed-by: Dylan Baker <dylan@pnwbakers>
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Signed-off-by: Eric Engestrom <[email protected]>
Reviwed-by: Dylan Baker <dylan@pnwbakers>
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As requested by Tim.
This was generated with:
grep 'PIPE_ARCH_.*_ENDIAN' -rIl | xargs sed -ie 's@PIPE_ARCH_\(.*\)_ENDIAN@UTIL_ARCH_\1_ENDIAN@'g
v2: - add this patch
Reviewed-by: Eric Engestrom <[email protected]>
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This will allow it to be used as a drop in replacement for
_mesa_little_endian in a number of cases.
v2: - Always define PIPE_ARCH_LITTLE_ENDIAN and PIPE_ARCH_BIG_ENDIAN,
define the one that reflects the host system to 1 and the other to 0
- replace all uses of #ifdef, #ifndef, and #if defined() with #if
and #if ! with PIPE_ARCH_*_ENDIAN
Reviewed-by: Eric Engestrom <[email protected]>
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Signed-off-by: Leo Liu <[email protected]>
Reviewed-by: Marek Olšák <[email protected]>
Cc: Marek Olšák <[email protected]>
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Fixes: 86786999189c43b4a2c8e1c1a18b55cd2f369fff "aco: implement VGPR spilling"
Reviewed-by: Rhys Perry <[email protected]>
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Fixes: 86786999189c43b4a2c8e1c1a18b55cd2f369fff "aco: implement VGPR spilling"
Reviewed-by: Rhys Perry <[email protected]>
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Fixes: 86786999189c43b4a2c8e1c1a18b55cd2f369fff "aco: implement VGPR spilling"
Reviewed-by: Rhys Perry <[email protected]>
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If an app first creates a compute pipeline with
VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT set, then re-compile it
without that flag, the driver should re-compile the compute shader.
Otherwise, it will return the unoptimized one.
Fixes: ce188813bfe ("radv: add initial support for VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT")
Signed-off-by: Samuel Pitoiset <[email protected]>
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
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The seccomp filter allows read/write, let us make sure nobody can
do anything with this.
Fixes: cff53da3748 "radv: enable secure compile support"
Reviewed-by: Timothy Arceri <[email protected]>
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idep_xmlconfig already covers that
Signed-off-by: Eric Engestrom <[email protected]>
Acked-by: Dylan Baker <[email protected]>
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Got some int->pointer warnings and 20 is not a valid pointer ....
Fixes: 2e3a635ee69 "radv: Add an early exit in the secure compile if we already have the cache entries."
Reviewed-by: Timothy Arceri <[email protected]>
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The resulting locale is not used for Vulkan, and it is not reference
counted, giving issues when multiple instances are created.
CC: 19.2 19.3 <[email protected]>
Reviewed-by: Lionel Landwerlin <[email protected]>
Reviewed-by: Samuel Pitoiset <[email protected]>
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Fixes the following building error:
external/mesa/src/amd/compiler/aco_spill.cpp:1768:
error: undefined reference to 'aco::lower_to_cssa(aco::Program*, aco::live&, radv_nir_compiler_options const*)'
Fixes: 0b8216b ("aco: Lower to CSSA")
Signed-off-by: Mauro Rossi <[email protected]>
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Do not need to declare it for other stages because this is for
streamout.
Signed-off-by: Samuel Pitoiset <[email protected]>
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
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libdrm returns -errno instead of directly the ioctl ret of -1.
Fixes: 1c3cda7d277 "radv: Add syncobj signal/reset/wait to winsys."
Reviewed-by: Samuel Pitoiset <[email protected]>
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Calculated the number for allocation and did not
reserve space ....
Fixes: 2117c53b723 "radv: Add temporary datastructure for submissions."
Reviewed-by: Samuel Pitoiset <[email protected]>
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VGPR spilling is implemented via MUBUF instructions and scratch memory.
Reviewed-by: Rhys Perry <[email protected]>
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This patch also moves private_segment_buffer and
scratch_offset to Program to easily access it.
Reviewed-by: Rhys Perry <[email protected]>
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Reviewed-by: Rhys Perry <[email protected]>
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Reviewed-by: Rhys Perry <[email protected]>
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Reviewed-by: Rhys Perry <[email protected]>
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Reviewed-by: Daniel Schürmann <[email protected]>
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Reviewed-by: Rhys Perry <[email protected]>
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predecessor
Reviewed-by: Rhys Perry <[email protected]>
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Reviewed-by: Rhys Perry <[email protected]>
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Variables spilled on both branch legs need to be assigned to the same spilling slot.
These affinities can be transitive through multiple merge blocks.
Reviewed-by: Rhys Perry <[email protected]>
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Reviewed-by: Rhys Perry <[email protected]>
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Reviewed-by: Rhys Perry <[email protected]>
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This patch makes the live variable analysis more precise
w.r.t. killed phi operands and the block's register pressure.
Reviewed-by: Rhys Perry <[email protected]>
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Converting to 'Conventional SSA Form' ensures correctness w.r.t. spilling of phi nodes.
Previously, it was possible that phi operands have intersecting live-ranges, and thus,
couldn't get spilled to the same spilling slot. For this reason, ACO tried to avoid to
spill phis, even if it was beneficial.
This patch implements a conversion pass which is currently only called if spilling is necessary.
Reviewed-by: Rhys Perry <[email protected]>
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Winsys semaphores without signal operation get silently ignored.
Not so for syncobjs, so actually signal them.
Fixes: 84d9551b232 "radv: Always enable syncobj when supported for all fences/semaphores."
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2030
Reviewed-by: Samuel Pitoiset <[email protected]>
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Closes: #1974
Signed-off-by: Rhys Perry <[email protected]>
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It was joining from the wrong blocks and block.kind is a bitmask instead
of an enum.
Reviewed-By: Timur Kristóf <[email protected]>
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Signed-off-by: Timur Kristóf <[email protected]>
Reviewed-by: Samuel Pitoiset <[email protected]>
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v2: remove accidental shaderInt16 change
v2: simplify can_move_down initialization
v2: simplify VMEM_CLAUSE_MAX_GRAB_DIST
Reviewed-by: Daniel Schürmann <[email protected]>
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Previously, the scheduler tried to move up instructions from below depending
VMEM instructions only to move them down again when scheduling the VMEM
instruction.
Reviewed-by: Rhys Perry <[email protected]>
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These got lost due to some refactoring.
Due to the way our scheduler works currently, for now
we add back the reorder flag for divergent loads only.
Reviewed-by: Rhys Perry <[email protected]>
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