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* amd/common: move ac_shader_{binary,reloc} into r600 and renameNicolai Hähnle2019-07-042-39/+0
* amd/common: removed unused ac_shader_binary functionsNicolai Hähnle2019-07-042-240/+0
* amd/common: remove unused ac_compile_module_to_binaryNicolai Hähnle2019-07-042-16/+0
* radv: Switch to using rtld.Bas Nieuwenhuizen2019-07-043-49/+35
* radv: Move more stuff to variant create time.Bas Nieuwenhuizen2019-07-042-61/+65
* radv: Add the concept of radv shader binaries.Bas Nieuwenhuizen2019-07-046-233/+346
* radv: Add export_prim_id to the shader variant info.Bas Nieuwenhuizen2019-07-043-2/+6
* radv: use last nir shader to determine stage in postprocessingBas Nieuwenhuizen2019-07-041-1/+1
* radv: Merge rsrc1/rsrc2 fields with the config fields.Bas Nieuwenhuizen2019-07-044-46/+39
* radv: do not crash when generating binning state for unknown chipsSamuel Pitoiset2019-07-041-22/+22
* radv: fix potential crash in the compute resolve pathSamuel Pitoiset2019-07-041-2/+3
* ac: rework ac_build_waitcnt for gfx10Marek Olšák2019-07-033-14/+49
* radeonsi/gfx10: set PA_SC_TILE_STEERING_OVERRIDEMarek Olšák2019-07-032-0/+3
* amd/common/gfx10: set DLC for llvm.amdgcn.s.buffer.loadNicolai Hähnle2019-07-031-3/+1
* radeonsi/gfx10: set DLC for loads when GLC is setMarek Olšák2019-07-033-12/+26
* radeonsi/gfx10: implement hardware MSAA resolveNicolai Hähnle2019-07-032-1/+2
* radeonsi/gfx10: implement gfx10_shader_nggNicolai Hähnle2019-07-031-0/+1
* ac/surface/gfx10: allow "rotated" micro modeNicolai Hähnle2019-07-032-8/+8
* ac/surface/gfx10: DCC is only supported with SW_64KB_{Z,R}_X modesNicolai Hähnle2019-07-031-3/+10
* amd/addrlib/gfx10: forbid DCC for swizzle modes which the hardware does not s...Nicolai Hähnle2019-07-031-3/+2
* amd/addrlib/gfx10: fix assertion in Addr2IsValidDisplaySwizzleModeNicolai Hähnle2019-07-031-0/+1
* amd/common/gfx10: print gfx10 registers in debug dumpsNicolai Hähnle2019-07-031-1/+3
* amd/common/gfx10: CMASK is only used for FMASKNicolai Hähnle2019-07-031-2/+3
* amd/common/gfx10: support new tbuffer encodingNicolai Hähnle2019-07-031-2/+45
* amd/common/gfx10: pad shader buffers for instruction prefetchNicolai Hähnle2019-07-031-0/+19
* amd/common/gfx10: implement scan & reduce operationsNicolai Hähnle2019-07-031-8/+104
* amd/common/gfx10: add GS_ALLOC_REQ message defineNicolai Hähnle2019-07-031-0/+1
* amd/common/gfx10: print out GCR_CNTL as part of {ACQUIRE,RELEASE}_MEMNicolai Hähnle2019-07-031-11/+17
* amd/common/gfx10: add register JSONNicolai Hähnle2019-07-038-23/+22377
* amd/common: add GFX10 chipsNicolai Hähnle2019-07-034-4/+25
* radv: gfx10 is not supportedNicolai Hähnle2019-07-031-0/+3
* amd/addrlib: add gfx10 supportMarek Olšák2019-07-0319-40/+12176
* radv: Support VK_EXT_queue_family_foreign.Bas Nieuwenhuizen2019-07-033-3/+7
* radv: Fix interactions between variable descriptor count and inline uniform b...Bas Nieuwenhuizen2019-07-031-1/+5
* radv: only allocate a 32-bit value for the TC-compat range metadataSamuel Pitoiset2019-07-031-2/+2
* radv: remove unused code in radv_update_tc_compat_zrange_metadata()Samuel Pitoiset2019-07-031-2/+0
* radv: add radv_get_depth_pipeline() helperSamuel Pitoiset2019-07-031-25/+41
* radv: enable DCC for layers on GFX8Samuel Pitoiset2019-07-021-9/+23
* radv: do not enable DCC for mipmapped arrays because performance is worseSamuel Pitoiset2019-07-021-0/+4
* radv: implement clearing DCC layers on GFX8Samuel Pitoiset2019-07-022-4/+7
* radv: merge radv_dcc_clear_level() into radv_clear_dcc()Samuel Pitoiset2019-07-021-30/+22
* radv: add support for decompressing DCC layers with computeSamuel Pitoiset2019-07-021-51/+53
* ac: compute the DCC fast clear size per slice on GFX8Samuel Pitoiset2019-07-022-0/+28
* ac: compute the size of one DCC slice on GFX8Samuel Pitoiset2019-07-022-0/+7
* radv: Only allocate supplied number of descriptors when variable.Bas Nieuwenhuizen2019-07-011-1/+7
* nir: Add lower_rotate flag and set to true in all driversSagar Ghuge2019-07-011-0/+1
* radv: rework how the number of VGPRs is computedSamuel Pitoiset2019-07-013-26/+31
* radv: gather if a vertex shaders needs the instance IDSamuel Pitoiset2019-07-011-4/+14
* radv: fix decompressing DCC levels with computeSamuel Pitoiset2019-07-011-1/+7
* radv: the number of VGPR_COMP_CNT for GS is expected to be 0 on GFX8Samuel Pitoiset2019-07-011-1/+1
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