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* amdgpu/addrlib: Pad pitch to multiples of 256 for DCC surface on FijiNicolai Hähnle2017-03-308-49/+131
| | | | | The change also modifies function CiLib::HwlPadDimensions to report adjusted pitch alignment.
* amdgpu/addrlib: Fix number of //Xavi Zhang2017-03-308-66/+66
| | | | | | Find ^/{80,99}$ and replace them to 100 "/" Signed-off-by: Nicolai Hähnle <[email protected]>
* amdgpu/addrlib: Cleanup.Nicolai Hähnle2017-03-3013-73/+68
| | | | Signed-off-by: Nicolai Hähnle <[email protected]>
* amdgpu/addrlib: Use namespacesXavi Zhang2017-03-3016-892/+969
| | | | Signed-off-by: Nicolai Hähnle <[email protected]>
* amdgpu/addrlib: Adjust 99 "*" to 100 "*" alignmentKevin Zhao2017-03-3018-895/+895
| | | | Signed-off-by: Nicolai Hähnle <[email protected]>
* amdgpu/addrlib: Add a new tile mode ADDR_TM_UNKNOWNFrans Gu2017-03-308-14/+211
| | | | | This can be used by address lib client to ask address lib to select tile mode.
* amdgpu/addrlib: Stylish cleanup.Xavi Zhang2017-03-305-17/+16
| | | | Signed-off-by: Nicolai Hähnle <[email protected]>
* amdgpu/addrlib: Disable tcComaptible when depth surface is not macro tiledRoy Zhan2017-03-301-17/+20
| | | | Experiment show 1D tiling + TcCompatible cannot work together.
* amdgpu/addrlib: fix pixel index calculation of thick micro tilingXavi Zhang2017-03-301-4/+4
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* amdgpu/addrlib: Add a flag to skip calculate indicesXavi Zhang2017-03-303-14/+21
| | | | | This is useful for debugging and special cases for stencil surfaces do not require texture fetch compatible.
* amdgpu/addrlib: add equation generationNicolai Hähnle2017-03-3012-118/+1344
| | | | | | | | | | | | | | | | 1. Add new surface flags needEquation for client driver use to force the surface tile setting equation compatible. Override 2D/3D macro tile mode to PRT_* tile mode if this flag is TRUE and num slice > 1. 2. Add numEquations and pEquationTable in ADDR_CREATE_OUTPUT structure to return number of equations and the equation table to client driver 3. Add equationIndex in ADDR_COMPUTE_SURFACE_INFO_OUTPUT structure to return the equation index to client driver Please note the use of address equation has following restrictions: 1) The surface can't be splitable 2) The surface can't have non zero tile swizzle value 3) Surface with > 1 slices must have PRT tile mode, which disable slice rotation
* amdgpu/addrlib: rename ComputeSurfaceThickness to ThicknessNicolai Hähnle2017-03-305-32/+32
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* amdgpu/addrlib: add define HAVE_TSERVERXavi Zhang2017-03-302-6/+6
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* amdgpu/addrlib: Add new interface to support macro mode index queryFrans Gu2017-03-304-0/+115
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* amdgpu/addrlib: add explicit Log2NonPow2 functionRoy Zhan2017-03-301-8/+20
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* amdgpu/addrlib: Fix invalid access to m_tileTableNicolai Hähnle2017-03-301-6/+17
| | | | | | | | Sometimes client driver passes valid tile info into address library, in this case, the tile index is computed in function HwlPostCheckTileIndex instead of CiAddrLib::HwlSetupTileCfg. We need to call HwlPostCheckTileIndex to calculate the correct tile index to get tile split bytes for this case.
* amdgpu/addrlib: add ADDR_ANALYSIS_ASSUMENicolai Hähnle2017-03-303-10/+20
| | | | It helps fix analysis warnings in MSC.
* amdgpu/addrlib: add tcCompatible htile addr from coordinate support.XiaoYuan Zheng2017-03-305-13/+80
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* amdgpu/addrlib: force all zero tile info for linear general.Carlos Xiong2017-03-301-1/+10
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* amdgpu/addrlib: Add a member "bpp" for input of method AddrConvertTileIndex ↵Nicolai Hähnle2017-03-307-32/+53
| | | | | | | | | | | and AddrConvertTileInfoToHW When clients queries tile Info from tile index and expects accurate tileSplit info, bits per pixel info is required to be provided since this is necessary for computing tileSplitBytes; otherwise Addrlib will return value of "tileBytes" instead if bpp is 0 - which is also current logic. If clients don't need tileSplit info, it's OK to pass bpp with value 0.
* amdgpu/addrlib: Refine the PRT tile mode selectionFrans Gu2017-03-302-51/+19
| | | | | Switch the tile index based on logic instead of hardcoded threshold for different ASIC.
* amdgpu/addrlib: add dccRamSizeAligned output flagXavi Zhang2017-03-302-1/+7
| | | | | This flag indicates to the client if this level's DCC memory is aligned or not. No aligned means there are padding to the end.
* amdgpu/addrlib: Change comment alignmentNicolai Hähnle2017-03-301-12/+12
| | | | Signed-off-by: Nicolai Hähnle <[email protected]>
* amdgpu/addrlib: style changes and minor cleanupsNicolai Hähnle2017-03-3011-84/+82
| | | | Signed-off-by: Nicolai Hähnle <[email protected]>
* amdgpu/addrlib: AddrLib inheritance refactorNicolai Hähnle2017-03-309-560/+675
| | | | | | Add one more abstraction layer into inheritance system. Signed-off-by: Nicolai Hähnle <[email protected]>
* amdgpu/addrlib: rearrange code in preparation of refactoringNicolai Hähnle2017-03-305-3528/+3595
| | | | | | No code changes. Signed-off-by: Nicolai Hähnle <[email protected]>
* amdgpu/addrlib: add disableLinearOpt flagXavi Zhang2017-03-303-3/+8
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* amdgpu/addrlib: Add GetMaxAlignmentsXavi Zhang2017-03-308-1/+184
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* amdgpu/addrlib: Let Kaveri go general stereo right eye offset padding pathXavi Zhang2017-03-304-54/+41
| | | | | | | | Kaveri (2-pipe) macro tiling mode table was initially set to all 4-aspect-ratio so the swizzling path did not work for it and then we chose to pad the offset. We now discover the root cause is that if ratio > 2, the swizzling path does not work. So we can safely use the same path for Kaveri.
* amdgpu/addrlib: Rewrite tile mode optmization codeXavi Zhang2017-03-306-27/+52
| | | | Note: remove reference to degrade4Space and use opt4Space instead.
* amdgpu/addrlib: Add a flag "tcCompatible" to surface info output structure.Carlos Xiong2017-03-303-15/+50
| | | | | | | Even if surface info input flag "tcComaptible" is enabled, tc compatible may be not supported if tile split happens for depth surfaces. Add a new flag in output structure to notify client to disable tc compatible in this case.
* amdgpu/addrlib: Make comments shorterXavi Zhang2017-03-301-47/+29
| | | | Signed-off-by: Nicolai Hähnle <[email protected]>
* amdgpu/addrlib: add new flag nonSplitXiaoYuan Zheng2017-03-302-2/+3
| | | | | Flag tcCompatible has different usage in CI and VI. Add a new flag "nonSplit" for CI.
* amdgpu/addrlib: allow tileSplitBytes greater than row sizeXiao-Tao Zai2017-03-301-1/+1
| | | | | | | Carrizo row size is 1K, while tileSplitBytes is 2K for a 4xAA 32bpp depth surface. Remove the sanity check that tileSplitBytes must be greater than row size. There could be performance loss but may be covered by non-split depth which enables tc-compatible read.
* amdgpu/addrlib: Change to compute TC compatible stencil infoCarlos Xiong2017-03-302-65/+59
| | | | | | | | | | | | Change the logic to compute tc compatible stencil info via depth's tileIndex instead of using depth's tileInfo. So the clients can get the stencil's tileInfo computed from macroModeTable. If the stencil tileInfo is same as depth tileInfo, then stencil is tc compatible; otherwise, stencil is not tc compatible. The current suggestion is to create another stencil buffer with the tc compatible tileInfo, use depth-to-color copy to decompress and tile convert the rendered stencil to tc compoatible stencil (And use the new stencil buffer to program TC).
* amdgpu/addrlib: rename SiAddrLib/CiAddrLib to match internal spellingNicolai Hähnle2017-03-304-149/+149
| | | | Signed-off-by: Nicolai Hähnle <[email protected]>
* radv: fix mask attribs properly.Dave Airlie2017-03-301-2/+2
| | | | | | some days it just doesn't pay to get out of bed. Signed-off-by: Dave Airlie <[email protected]>
* radv: fix regression with mask attrib setting code.Dave Airlie2017-03-301-3/+3
| | | | Signed-off-by: Dave Airlie <[email protected]>
* radv: move to using nir clip/cull merge pass.Dave Airlie2017-03-302-112/+40
| | | | | | | | | | Doing this before tessellation makes doing some bits of tessellation a bit cleaner. It also cleans up a bit of the llvm generator code. Reviewed-by: Edward O'Callaghan <[email protected]> Acked-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: Enable sparseBinding feature.Bas Nieuwenhuizen2017-03-291-4/+8
| | | | | Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv/amdgpu: Use reference counting for bos.Bas Nieuwenhuizen2017-03-292-0/+11
| | | | | | | | | | | | | Per the Vulkan spec, memory objects may be deleted before the buffers and images using them are deleted, although those resources then cannot be used except for deletion themselves. For the virtual buffers, we need to access them on resource destruction to unmap the regions, so this results in a use-after-free. Implement reference counting to avoid this. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: Implement sparse memory binding.Bas Nieuwenhuizen2017-03-291-4/+80
| | | | | | | v2: Only submit when semaphores are specified. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: Implement sparse image creation.Bas Nieuwenhuizen2017-03-292-2/+22
| | | | | Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: Implement sparse buffer creation.Bas Nieuwenhuizen2017-03-292-2/+21
| | | | | Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv/amdgpu: Add winsys implementation of virtual buffers.Bas Nieuwenhuizen2017-03-294-26/+349
| | | | | | | | | v2: - Added comments. - Fixed a double unmap bug. - Actually unmap the non-edge old ranges. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: Assert when setting 0 registers in a sequence.Bas Nieuwenhuizen2017-03-291-0/+4
| | | | | | | To catch more of those hangs early. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Acked-by: Dave Airlie <[email protected]>
* radv: only emit ps_input_cntl is we have any to outputDave Airlie2017-03-281-3/+6
| | | | | | | Otherwise we get GPU hangs. Reported-by: Alex Smith <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: move shader stages calculation to pipeline.Dave Airlie2017-03-283-9/+10
| | | | | | | | With tess this becomes a bit more complex. so move to pipeline for now. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: move pa_cl_vs_out_cntl calculation to pipelineDave Airlie2017-03-283-17/+32
| | | | | | | This also takes the side band setting code from radeonsi. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: move calculating fragment shader i/os to pipeline.Dave Airlie2017-03-283-63/+77
| | | | | | | There is no need to calculate this on each command submit. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
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