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* amdgpu/addrlib: add dccRamSizeAligned output flagXavi Zhang2017-03-302-1/+7
| | | | | This flag indicates to the client if this level's DCC memory is aligned or not. No aligned means there are padding to the end.
* amdgpu/addrlib: Change comment alignmentNicolai Hähnle2017-03-301-12/+12
| | | | Signed-off-by: Nicolai Hähnle <[email protected]>
* amdgpu/addrlib: style changes and minor cleanupsNicolai Hähnle2017-03-3011-84/+82
| | | | Signed-off-by: Nicolai Hähnle <[email protected]>
* amdgpu/addrlib: AddrLib inheritance refactorNicolai Hähnle2017-03-309-560/+675
| | | | | | Add one more abstraction layer into inheritance system. Signed-off-by: Nicolai Hähnle <[email protected]>
* amdgpu/addrlib: rearrange code in preparation of refactoringNicolai Hähnle2017-03-305-3528/+3595
| | | | | | No code changes. Signed-off-by: Nicolai Hähnle <[email protected]>
* amdgpu/addrlib: add disableLinearOpt flagXavi Zhang2017-03-303-3/+8
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* amdgpu/addrlib: Add GetMaxAlignmentsXavi Zhang2017-03-308-1/+184
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* amdgpu/addrlib: Let Kaveri go general stereo right eye offset padding pathXavi Zhang2017-03-304-54/+41
| | | | | | | | Kaveri (2-pipe) macro tiling mode table was initially set to all 4-aspect-ratio so the swizzling path did not work for it and then we chose to pad the offset. We now discover the root cause is that if ratio > 2, the swizzling path does not work. So we can safely use the same path for Kaveri.
* amdgpu/addrlib: Rewrite tile mode optmization codeXavi Zhang2017-03-306-27/+52
| | | | Note: remove reference to degrade4Space and use opt4Space instead.
* amdgpu/addrlib: Add a flag "tcCompatible" to surface info output structure.Carlos Xiong2017-03-303-15/+50
| | | | | | | Even if surface info input flag "tcComaptible" is enabled, tc compatible may be not supported if tile split happens for depth surfaces. Add a new flag in output structure to notify client to disable tc compatible in this case.
* amdgpu/addrlib: Make comments shorterXavi Zhang2017-03-301-47/+29
| | | | Signed-off-by: Nicolai Hähnle <[email protected]>
* amdgpu/addrlib: add new flag nonSplitXiaoYuan Zheng2017-03-302-2/+3
| | | | | Flag tcCompatible has different usage in CI and VI. Add a new flag "nonSplit" for CI.
* amdgpu/addrlib: allow tileSplitBytes greater than row sizeXiao-Tao Zai2017-03-301-1/+1
| | | | | | | Carrizo row size is 1K, while tileSplitBytes is 2K for a 4xAA 32bpp depth surface. Remove the sanity check that tileSplitBytes must be greater than row size. There could be performance loss but may be covered by non-split depth which enables tc-compatible read.
* amdgpu/addrlib: Change to compute TC compatible stencil infoCarlos Xiong2017-03-302-65/+59
| | | | | | | | | | | | Change the logic to compute tc compatible stencil info via depth's tileIndex instead of using depth's tileInfo. So the clients can get the stencil's tileInfo computed from macroModeTable. If the stencil tileInfo is same as depth tileInfo, then stencil is tc compatible; otherwise, stencil is not tc compatible. The current suggestion is to create another stencil buffer with the tc compatible tileInfo, use depth-to-color copy to decompress and tile convert the rendered stencil to tc compoatible stencil (And use the new stencil buffer to program TC).
* amdgpu/addrlib: rename SiAddrLib/CiAddrLib to match internal spellingNicolai Hähnle2017-03-304-149/+149
| | | | Signed-off-by: Nicolai Hähnle <[email protected]>
* radv: fix mask attribs properly.Dave Airlie2017-03-301-2/+2
| | | | | | some days it just doesn't pay to get out of bed. Signed-off-by: Dave Airlie <[email protected]>
* radv: fix regression with mask attrib setting code.Dave Airlie2017-03-301-3/+3
| | | | Signed-off-by: Dave Airlie <[email protected]>
* radv: move to using nir clip/cull merge pass.Dave Airlie2017-03-302-112/+40
| | | | | | | | | | Doing this before tessellation makes doing some bits of tessellation a bit cleaner. It also cleans up a bit of the llvm generator code. Reviewed-by: Edward O'Callaghan <[email protected]> Acked-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: Enable sparseBinding feature.Bas Nieuwenhuizen2017-03-291-4/+8
| | | | | Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv/amdgpu: Use reference counting for bos.Bas Nieuwenhuizen2017-03-292-0/+11
| | | | | | | | | | | | | Per the Vulkan spec, memory objects may be deleted before the buffers and images using them are deleted, although those resources then cannot be used except for deletion themselves. For the virtual buffers, we need to access them on resource destruction to unmap the regions, so this results in a use-after-free. Implement reference counting to avoid this. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: Implement sparse memory binding.Bas Nieuwenhuizen2017-03-291-4/+80
| | | | | | | v2: Only submit when semaphores are specified. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: Implement sparse image creation.Bas Nieuwenhuizen2017-03-292-2/+22
| | | | | Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: Implement sparse buffer creation.Bas Nieuwenhuizen2017-03-292-2/+21
| | | | | Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv/amdgpu: Add winsys implementation of virtual buffers.Bas Nieuwenhuizen2017-03-294-26/+349
| | | | | | | | | v2: - Added comments. - Fixed a double unmap bug. - Actually unmap the non-edge old ranges. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: Assert when setting 0 registers in a sequence.Bas Nieuwenhuizen2017-03-291-0/+4
| | | | | | | To catch more of those hangs early. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Acked-by: Dave Airlie <[email protected]>
* radv: only emit ps_input_cntl is we have any to outputDave Airlie2017-03-281-3/+6
| | | | | | | Otherwise we get GPU hangs. Reported-by: Alex Smith <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: move shader stages calculation to pipeline.Dave Airlie2017-03-283-9/+10
| | | | | | | | With tess this becomes a bit more complex. so move to pipeline for now. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: move pa_cl_vs_out_cntl calculation to pipelineDave Airlie2017-03-283-17/+32
| | | | | | | This also takes the side band setting code from radeonsi. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: move calculating fragment shader i/os to pipeline.Dave Airlie2017-03-283-63/+77
| | | | | | | There is no need to calculate this on each command submit. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: move shader_z_format calculation to pipeline.Dave Airlie2017-03-283-4/+8
| | | | | | | No need to recalculate this every time. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: move db_shader_control calculation to pipeline.Dave Airlie2017-03-283-16/+20
| | | | | | | There is no need to recalculate this every time. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: move vgt_gs_mode value to pipeline.Dave Airlie2017-03-283-27/+30
| | | | | | | No need to recalculate this everytime. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: add parameter to emit_waitcnt.Dave Airlie2017-03-281-3/+8
| | | | | | | | This is just a precursor for tess support, which needs to pass different values here. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: rework vertex/export shader output handlingDave Airlie2017-03-284-70/+86
| | | | | | | | | In order to faciliate adding tess support, split the vs/es output info into a separate block, so we make it easier to have the tess shaders export the same info. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: fix ia_multi_vgt_param for instanced vs indirect draw.Dave Airlie2017-03-283-13/+15
| | | | | | | | The logic was different than radeonsi, fix it up before adding tess support. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: handle NULL multisample state.Dave Airlie2017-03-281-8/+12
| | | | | | | | If rasterization is disabled, we can get a NULL multisample state. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: flush DB cache before and after HTILE decompress.Bas Nieuwenhuizen2017-03-281-0/+6
| | | | | | | | | | | It reads @ writes the DB cache, and we haven't flushed dst caches yet, so DB cache may be stale. Also the user might be shader read (and probably is), so also flush after. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]> CC: <[email protected]> Fixes: f4e499ec791 ("radv: add initial non-conformant radv vulkan driver")
* radv: don't emit no color formats. (v3)Dave Airlie2017-03-281-2/+19
| | | | | | | | | | | | | | | If we had no rasterization, we'd emit SPI color format as all 0's the hw dislikes this, add the workaround from radeonsi. Found while debugging tessellation v2: handle at pipeline stage, we have to handle it after we process the fragment shader. (Bas) v3: simplify even further, remove old fallback. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: Invalidate L2 for TRANSFER_WRITE barriersAlex Smith2017-03-231-1/+1
| | | | | | | | | | | | CP DMA and PKT3_WRITE_DATA (in CmdUpdateBuffer) don't (currently) write through L2. Therefore, to make these writes visible to later accesses we must invalidate L2 rather than just writing it back, to avoid the possibility that stale data is read through L2. Cc: "17.0" <[email protected]> Signed-off-by: Alex Smith <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: consistently use ifndef guards over pragma onceEmil Velikov2017-03-221-1/+4
| | | | | | | | | | Namely: annotate the single file which is not using a ifndef guard - vk_format.h Signed-off-by: Emil Velikov <[email protected]> Acked-by: Vedran Miletić <[email protected]> Acked-by: Juha-Pekka Heikkila <[email protected]> Reviewed-by: Edward O'Callaghan <[email protected]>
* ac: consistently use ifndef guards over pragma onceEmil Velikov2017-03-223-3/+12
| | | | | | | | Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Acked-by: Vedran Miletić <[email protected]> Acked-by: Juha-Pekka Heikkila <[email protected]> Reviewed-by: Edward O'Callaghan <[email protected]>
* ac: fix build with LLVM 5.0svnMarek Olšák2017-03-221-2/+8
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: move KHR_get_physical_device_properties2 to instance props.Dave Airlie2017-03-211-4/+4
| | | | | | | | | This is an instance property not a device one. Fixes: dEQP-VK.api.info.device.extensions Signed-off-by: Dave Airlie <[email protected]>
* radv: drop illegal DB format error.Dave Airlie2017-03-211-3/+0
| | | | | | We'll get this if we have a stencil only setup. Signed-off-by: Dave Airlie <[email protected]>
* radv: fix logic for when to flush on multiple CS emissionDave Airlie2017-03-201-8/+8
| | | | | | | | | The current code evaluated to always true, we only want to flush on the first submit. Rename the variable to do_flush, and only emit on the first iteration. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv/meta: fix image clears for r4g4 format.Dave Airlie2017-03-201-0/+8
| | | | | | | This just uses an 8-bit clear and packs the values. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* Revert "radv: fallback to an in-memory cache when no pipline cache is provided"Dave Airlie2017-03-203-13/+6
| | | | | | | | | | | This reverts commit 2845a108a9a8bd4b0e6e9b590c976452fb99eb10. This break VK-GL-CTS randomly. ./deqp-vk --deqp-case=dEQP-VK.texture.filtering.3d.formats.r4g4b4a4* bounces around here from 6/6 to 3/6 or 4/6 to hanging. Signed-off-by: Dave Airlie <[email protected]>
* radv: fix primitive reset index emissionDave Airlie2017-03-201-1/+1
| | | | | | | | | | This was meant to be checking the index type to get the correct index not the last emitted one. This fixes: dEQP-VK.pipeline.input_assembly.primitive_restart.index_type_uint32.triangle_strip_with_adjacency Reviewed-by: Bas Nieuwenhuizen <[email protected]> Cc: "13.0 17.0" <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv/ac: Fix shared memory offset calculationAlex Smith2017-03-171-1/+1
| | | | | | | | | | | The index passed to get_shared_memory_ptr is an attribute slot index, i.e. the index of a vec4 within LDS. Therefore this must be scaled by sizeof(vec4) to give the LDS byte offset. Fixes: f4e499ec791 ("radv: add initial non-conformant radv vulkan driver") Signed-off-by: Alex Smith <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> CC: <[email protected]>
* radv: Fix using more than 4 bound descriptor setsJames Legg2017-03-171-1/+3
| | | | | | | | Avoid a buffer overflow in ac_nir_to_llvm.c's create_function when using more than 4 descriptor sets. radv claims support for 8. Cc: 17.0 <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
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