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* radv: enable POLARIS12 support.Dave Airlie2017-05-054-0/+8
| | | | | | | | | | | This just adds the chip in the right places. We don't set the partial_vs_wave workaround, as radeonsi doesn't, but have to confirm it's not required. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Cc: "17.1" <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radeonsi: drop support for LLVM 3.8Marek Olšák2017-05-052-133/+53
| | | | | | | | | | | | LLVM 3.8: - had broken indirect resource indexing - didn't have scratch coalescing - was the last user of problematic v16i8 - only supported OpenGL 4.1 This leaves us with LLVM 3.9 and LLVM 4.0 support for Mesa 17.2. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: stop using v16i8Marek Olšák2017-05-051-1/+1
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: make some PA & DB registers match the closed Vulkan driverMarek Olšák2017-05-051-0/+4
| | | | | Cc: 17.1 <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radv: don't advertise transfer props unless we can do anything elseDave Airlie2017-05-051-2/+2
| | | | | | | | | There is no reason to advertise transfer ability for formats we can't use for anything else. This stops some CTS tests hitting internal error for 64-bit types when they see the transfer flags. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: Don't use FLAT_SHADE for constants.Bas Nieuwenhuizen2017-05-041-4/+4
| | | | | | | | | Setting both offset to 0x20 and flat shade results in passthrough mode instead of the constant. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]> Fixes: f205e19e4f8 "radv/ac: eliminate unused vertex shader outputs. (v2)"
* radv: don't leak DRM devicesGrazvydas Ignotas2017-05-031-1/+3
| | | | | | | | After successful drmGetDevices2() call, drmFreeDevices() needs to be called. Fixes: 743315f2 "radv: do not open random render node(s)" Signed-off-by: Grazvydas Ignotas <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: fix possible stack corruptionGrazvydas Ignotas2017-05-031-1/+1
| | | | | | | | | | drmGetDevices2 takes count and not size. Probably hasn't caused problems yet in practice and was missed as setups with more than 8 DRM devices are not very common. Fixes: 743315f2 "radv: do not open random render node(s)" Signed-off-by: Grazvydas Ignotas <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* ac: eliminate duplicated VS exportsMarek Olšák2017-05-031-2/+79
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Only very few shaders have them (from 48486 shaders): shaders/private/left_4_dead_2/765.shader_test - ac: 1 matches 2 shaders/private/left_4_dead_2/877.shader_test - ac: 1 matches 6 shaders/private/left_4_dead_2/2141.shader_test - ac: 1 matches 6 shaders/private/ue4_effects_cave/11.shader_test - ac: 4 matches 5 shaders/private/ue4_effects_cave/14.shader_test - ac: 5 matches 6 shaders/private/ue4_effects_cave/46.shader_test - ac: 5 matches 6 shaders/private/ue4_effects_cave/42.shader_test - ac: 4 matches 5 shaders/private/ue4_effects_cave/104.shader_test - ac: 4 matches 5 shaders/private/f1-2015/336.shader_test - ac: 3 matches 4 shaders/private/f1-2015/948.shader_test - ac: 6 matches 7 shaders/private/f1-2015/602.shader_test - ac: 0 matches 3 shaders/private/f1-2015/600.shader_test - ac: 0 matches 3 shaders/private/f1-2015/1214.shader_test - ac: 0 matches 1 shaders/private/f1-2015/988.shader_test - ac: 4 matches 5 shaders/private/ue4_elemental/149.shader_test - ac: 3 matches 4 shaders/private/ue4_elemental/346.shader_test - ac: 4 matches 5 shaders/private/ue4_elemental/178.shader_test - ac: 3 matches 4 shaders/private/ue4_elemental/136.shader_test - ac: 4 matches 5 shaders/private/ue4_elemental/168.shader_test - ac: 4 matches 5 shaders/private/ue4_elemental/690.shader_test - ac: 3 matches 4 shaders/private/ue4_elemental/19.shader_test - ac: 5 matches 6 shaders/private/dota2/1901.shader_test - ac: 0 matches 5 shaders/private/dota2/1357.shader_test - ac: 0 matches 5 shaders/private/dota2/1375.shader_test - ac: 0 matches 5 shaders/private/dota2/1369.shader_test - ac: 0 matches 5 shaders/private/dota2/1583.shader_test - ac: 0 matches 5 shaders/private/dota2/1811.shader_test - ac: 0 matches 5 shaders/private/dota2/1893.shader_test - ac: 0 matches 5 shaders/private/dota2/1533.shader_test - ac: 0 matches 5 shaders/private/dota2/1951.shader_test - ac: 0 matches 5 shaders/private/dota2/1361.shader_test - ac: 0 matches 5 shaders/private/mad_max/2792.shader_test - ac: 0 matches 1 shaders/private/mad_max/2794.shader_test - ac: 0 matches 1 shaders/private/mad_max/2780.shader_test - ac: 0 matches 1 shaders/private/mad_max/2902.shader_test - ac: 0 matches 1 shaders/private/bioshock-infinite/3050.shader_test - ac: 3 matches 7 shaders/private/bioshock-infinite/2544.shader_test - ac: 3 matches 6 shaders/private/bioshock-infinite/3062.shader_test - ac: 3 matches 8 shaders/private/bioshock-infinite/2012.shader_test - ac: 3 matches 7 shaders/private/bioshock-infinite/3058.shader_test - ac: 3 matches 7 shaders/private/bioshock-infinite/3270.shader_test - ac: 3 matches 7 shaders/private/bioshock-infinite/732.shader_test - ac: 3 matches 7 shaders/private/bioshock-infinite/3026.shader_test - ac: 3 matches 7 shaders/private/bioshock-infinite/3258.shader_test - ac: 3 matches 6 shaders/private/bioshock-infinite/3198.shader_test - ac: 3 matches 6 shaders/private/bioshock-infinite/3046.shader_test - ac: 3 matches 7 shaders/private/bioshock-infinite/3168.shader_test - ac: 3 matches 6 shaders/private/bioshock-infinite/2550.shader_test - ac: 3 matches 6 shaders/private/bioshock-infinite/3210.shader_test - ac: 3 matches 6 shaders/private/bioshock-infinite/3032.shader_test - ac: 3 matches 6 shaders/private/bioshock-infinite/668.shader_test - ac: 3 matches 7 Reviewed-by: Dave Airlie <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* ac: rename ac_eliminate_const_vs_outputs -> ac_optimize_vs_outputsMarek Olšák2017-05-033-15/+15
| | | | | Reviewed-by: Dave Airlie <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* ac: first parse VS exports before eliminating constant onesMarek Olšák2017-05-031-24/+58
| | | | | | | A later commit will make use of this. Reviewed-by: Dave Airlie <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radv/ac: canonicalize the output for 32-bit float min/max.Dave Airlie2017-05-031-0/+8
| | | | | | | | | | | | | | | | | | This fixes: dEQP-VK.glsl.builtin.precision.min.* dEQP-VK.glsl.builtin.precision.max.* dEQP-VK.glsl.builtin.precision.clamp.* The problem is the hw doesn't compare denorms properly, so we have to flush them, even though the spec says flushing is optional, if you don't flush the results should be correct. The -pro driver changes the shader float mode, it would be nice if llvm could grow that perhaps. Acked-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: flush f32->f16 conversion denormals to zero. (v2)Dave Airlie2017-05-032-4/+41
| | | | | | | | | | | | | | | SPIR-V defines the f32->f16 operation as flushing denormals to 0, this compares the class using amd class opcode. Thanks to Matt Arsenault for figuring it out. This fix is VI+ only, add a TODO for SI/CIK. This fixes: dEQP-VK.spirv_assembly.instruction.compute.opquantize.flush_to_zero Acked-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: Add userspace fence buffer per context.Bas Nieuwenhuizen2017-05-034-37/+44
| | | | | | | | | | Having it in the winsys didn't work when multiple devices use the same winsys, as we then have multiple contexts per queue, and each context counts separately. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]> Fixes: 7b9963a28f4 "radv: Enable userspace fence checking."
* radv: enable lower_sub to fix loop unrolling.Dave Airlie2017-05-031-0/+1
| | | | | | | | | | Loop unroll asserts if it hits a sub, we don't really want to lower subs as llvm handles these things, but do this for now, until we can fix loop unroll to work with subs. Fixes: 14ae0bfa5 (radv: Add NIR loop unrolling) Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: Don't set dynamic state for pipelines with rasterizer dicard.Bas Nieuwenhuizen2017-05-031-6/+9
| | | | | | | | | | | | All of the dynamic states apply to rasterization & fragment processing, so we don't need to set them if we don't rasterize. We don't clear the dirty flags for them though, so we don't miss any updates for the next pipeline with rasterization. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]> Fixes: 76603aa90b8 "radv: Drop the default viewport when 0 viewports are given."
* radv: flush more stages when semaphore are waiting.Dave Airlie2017-05-032-3/+23
| | | | | | | | | | | | | | | This still doesn't give us complete pWaitDstStageMask support, but it should provide enough to be correct if not as efficent as possible. If we have wait semaphores we must flush between submits and flush the shaders as well. This fixes the remaining fails in: dEQP-VK.synchronization.op.single_queue.semaphore.*ssbo* Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: fix stencil only clears.Dave Airlie2017-05-031-0/+3
| | | | | | | | | | | | | | | If we are clearing stencil only, we still need to provide a a valid Z output from the vertex shader, we can't rely on the depth clear value having any meaning, as we use this for the position output, and it could get clipped, so we don't end up clearing anything. Fixes: dEQP-VK.renderpass.simple.stencil since I added S8 support. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv/wsi: report presentation error per image requestDave Airlie2017-05-031-6/+13
| | | | | | | | | | | | This ports 0fcb92c17dee681bd39c08ddf0abc358a27337c7 anv: wsi: report presentation error per image request This fixes: dEQP-VK.wsi.xlib.incremental_present.scale_none.* Reviewed-by: Daniel Stone <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: minor pahole related improvements.Dave Airlie2017-05-033-5/+5
| | | | | | | This just reduces the structs by 4-8 bytes each. Reviewed-by: Timothy Arceri <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv/image: resize some surface members.Dave Airlie2017-05-031-3/+3
| | | | | | | Oops meant to be part of previous series. Reviewed-by: Timothy Arceri <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: drop unused surface level members.Dave Airlie2017-05-032-6/+0
| | | | | Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv/image: drop blk_dDave Airlie2017-05-033-3/+1
| | | | | | | This was pretty much unused. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: remove some members of radeon surface.Dave Airlie2017-05-034-48/+40
| | | | | | | | We would be storing this info twice per image, no need to, remove it from the surface struct. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: move some image info into a separate struct.Dave Airlie2017-05-0313-80/+90
| | | | | | | This is to rework the surface code like radeonsi. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: provide a helper for comparing an image extents.Dave Airlie2017-05-032-2/+11
| | | | | | | | This just makes it easier to do the follow in cleanups of the surface. Reviewed-by: Timothy Arceri <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: Use correct stage for ready bit.Bas Nieuwenhuizen2017-05-021-9/+24
| | | | | | | | Set the bit in the same stage as the timestamp, instead always at top of pipe. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]> Tested-by: Grazvydas Ignotas <[email protected]>
* radv: Add top of pipe timestamp queries.Bas Nieuwenhuizen2017-05-022-12/+27
| | | | | | | Does not fix brokenness with the ready bit. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: Add NIR loop unrolling.Bas Nieuwenhuizen2017-05-021-0/+10
| | | | | | | | Not much effect on dota2/talos, but positive on deferred. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Timothy Arceri <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* ac: automake: sort sources list alphabeticallyEmil Velikov2017-04-281-3/+3
| | | | Signed-off-by: Emil Velikov <[email protected]>
* ac: include all sources in the tarballEmil Velikov2017-04-281-0/+1
| | | | | Fixes: e2659176cef ("radeonsi/ac: move vertex export remove to common code.") Signed-off-by: Emil Velikov <[email protected]>
* radeon/ac: remove assert causing regressionDave Airlie2017-04-271-1/+0
| | | | | | | | | | This assert wasn't in the original radeonsi code but I added it without totally understanding the original code, it caused some regressions in variable-indexing tessellation shaders. Fixes: e2659176 radeonsi/ac: move vertex export remove to common code. Reported-by: Michel Dänzer <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radeon/ac: fix build on llvm 3.8.1Dave Airlie2017-04-271-0/+1
| | | | | | Add missing include to fix build. Signed-off-by: Dave Airlie <[email protected]>
* radv/ac: eliminate unused vertex shader outputs. (v2)Dave Airlie2017-04-273-21/+45
| | | | | | | | | | | This is ported from radeonsi, and I can see at least one Talos shader drops an export due to this, and saves some VGPR usage. v2: use shared code. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radeonsi/ac: move vertex export remove to common code.Dave Airlie2017-04-275-1/+221
| | | | | | | | | | | This code can be shared by radv, we bump the max to VARYING_SLOT_MAX here, but that shouldn't have too much fallout. Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: fix regression in descriptor set freeing.Dave Airlie2017-04-271-1/+1
| | | | | | | | | | | Since the host pool changes, Fixes: dEQP-VK.api.descriptor_pool.out_of_pool_memory Fixes: 126d5ad "radv: Use host memory pool for non-freeable descriptors." Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: Enable userspace fence checking.Bas Nieuwenhuizen2017-04-263-3/+36
| | | | | | | | | | v2: - Added some error handling. - memset the buffer to 0. v3: Added assert for buffer size. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv/ac: setup mrt exports then export them in one go. (v2)Dave Airlie2017-04-251-15/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Noticed while looking at Sascha Willems deferred shaders. This is a bit of an llvm workaround, llvm was producing this: v_cvt_pkrtz_f16_f32_e64 v4, v7, v8 ; D2960004 00021107 v_cvt_pkrtz_f16_f32_e64 v6, v9, 1.0 ; D2960006 0001E509 s_waitcnt vmcnt(0) ; BF8C0F70 exp mrt0 v4, v4, v6, v6 compr ; C400040F 00000604 s_waitcnt expcnt(0) ; BF8C0F0F v_cvt_pkrtz_f16_f32_e64 v4, v12, v5 ; D2960004 00020B0C v_cvt_pkrtz_f16_f32_e64 v5, v14, 1.0 ; D2960005 0001E50E exp mrt1 v4, v4, v5, v5 compr ; C400041F 00000504 s_waitcnt expcnt(0) ; BF8C0F0F v_cvt_pkrtz_f16_f32_e64 v0, v0, v1 ; D2960000 00020300 v_cvt_pkrtz_f16_f32_e64 v1, v2, v3 ; D2960001 00020702 exp mrt2 v0, v0, v1, v1 done compr vm ; C4001C2F 00000100 After this change: v_cvt_pkrtz_f16_f32_e64 v4, v7, v8 ; D2960004 00021107 s_waitcnt vmcnt(0) ; BF8C0F70 v_cvt_pkrtz_f16_f32_e64 v0, v0, v1 ; D2960000 00020300 v_cvt_pkrtz_f16_f32_e64 v6, v9, 1.0 ; D2960006 0001E509 v_cvt_pkrtz_f16_f32_e64 v5, v12, v5 ; D2960005 00020B0C v_cvt_pkrtz_f16_f32_e64 v7, v14, 1.0 ; D2960007 0001E50E exp mrt0 v4, v4, v6, v6 compr ; C400040F 00000604 v_cvt_pkrtz_f16_f32_e64 v1, v2, v3 ; D2960001 00020702 exp mrt1 v5, v5, v7, v7 compr ; C400041F 00000705 exp mrt2 v0, v0, v1, v1 done compr vm ; C4001C2F 00000100 No waitcnt for exports are emitted. v2: fixup index->mrt mapping (Bas). Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv/ac: overhaul vs output/ps input routingDave Airlie2017-04-253-37/+55
| | | | | | | | In order to cleanly eliminate exports rewrite the code first to mirror how radeonsi works for now. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv/ac: move point coord after layer/viewport.Dave Airlie2017-04-251-6/+7
| | | | | | | | These need to be ordered as per shader enum ordering, I'll rewrite this soon, but this is a bug fix. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* android: radv/ac: Fix nir.h includeMauro Rossi2017-04-241-0/+2
| | | | | | | | | | | | | | Fixes following building errors due to missing include paths: external/mesa/src/amd/common/ac_shader_info.c:23:10: fatal error: 'nir/nir.h' file not found ^ external/mesa/src/compiler/nir/nir.h:48:10: fatal error: 'nir_opcodes.h' file not found ^ Fixes: 224cf29 "radv/ac: add initial pre-pass for shader info gathering" Acked-by: Dave Airlie <[email protected]> Acked-by: Emil Velikov <[email protected]>
* radv/ac: copy llvm machine feature flags from radeonsi.Dave Airlie2017-04-241-1/+1
| | | | | | | | This just updates this to use the same flags as radeonsi for consistency. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: Enable lowering fdiv in nir.Bas Nieuwenhuizen2017-04-231-0/+1
| | | | | | | Results in faster code than the lowering by LLVM. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: Use the correct pipeline for dispatches.Bas Nieuwenhuizen2017-04-221-3/+3
| | | | | | | Signed-off-by: Bas Nieuwenhuizen <[email protected]> Fixes: ec15e0d30 "radv: optimise compute shader grid size emission." Tested-by: Grazvydas Ignotas <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: Prefetch compute shader too.Bas Nieuwenhuizen2017-04-211-0/+1
| | | | | | | For consistency, doesn't really impact performance. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv/ac: use tex_lz if we can.Dave Airlie2017-04-201-6/+16
| | | | | | | | Looking at some Talos shaders vs radeonsi, I noticed they use tex_lz in a few places, so we should be able to as well. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* ac: fix build after LLVM 5.0 SVN r300718Christoph Haag2017-04-201-0/+4
| | | | | | | | v2: previously getWithDereferenceableBytes() exists, but addAttr() doesn't take that type Signed-off-by: Christoph Haag <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]> Tested-and-reviewed-by: Mike Lothian <[email protected]>
* radv: Set variant code_size when created from the cache.Bas Nieuwenhuizen2017-04-201-0/+1
| | | | | Signed-off-by: Bas Nieeuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: Add shader prefetch.Bas Nieuwenhuizen2017-04-193-0/+18
| | | | | | | | | | Gives me approximately a 2% perf increase in bot dota2 & talos. Having descriptors (both sets and vertex buffers) prefetched didn't help so I didn't include that. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: Remove binding buffer count.Bas Nieuwenhuizen2017-04-193-13/+10
| | | | | | | In cases where it is used it is always 1. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
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