summaryrefslogtreecommitdiffstats
path: root/src/amd
Commit message (Collapse)AuthorAgeFilesLines
* radv/ws: get rid of useless return valueDave Airlie2018-01-181-3/+2
| | | | | | | This also used boolean, so nice to kill that. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: Initialize DCC on transition from preinitialized.Bas Nieuwenhuizen2018-01-181-1/+3
| | | | | | | | | Looks like the decompress does not handle invalid encodings well, which happens with random memory. Of course apps should not use it with random memory, but they are allowed to .... Fixes: 44fcf58744 "radv: Disable DCC for GENERAL layout and compute transfer dest." Reviewed-by: Dave Airlie <[email protected]>
* ac: fix buffer overflow bug in 64bit SSBO loadsTimothy Arceri2018-01-181-1/+4
| | | | | | Fixes: 441ee1e65b04 "radv/ac: Implement Float64 SSBO loads" Reviewed-by: Marek Olšák <[email protected]>
* ac: fix nir_intrinsic_get_buffer_size for radeonsiTimothy Arceri2018-01-181-2/+2
| | | | | Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* ac: rework load_tcs_{inputs,outputs}Timothy Arceri2018-01-181-73/+53
| | | | | | | This shares more code and calls the new shared load_tess_varyings() abi so that the radeonsi nir path now supports tcs output loads. Reviewed-by: Nicolai Hähnle <[email protected]>
* ac/radeonsi: add tcs load outputs supportTimothy Arceri2018-01-182-19/+22
| | | | | | | | | The code to load outputs is essentially the same as load inputs so we make the interface more generic to maximise code sharing. We will make use of the new support in the following patch. Reviewed-by: Nicolai Hähnle <[email protected]>
* radv: Implement VK_EXT_debug_report.Bas Nieuwenhuizen2018-01-173-0/+50
| | | | | | | | This is not hooked up to any messages yet, but useful for e.g. renderdoc if you add some messages during development. Reviewed-by: Dave Airlie <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* ac: set no-signed-zeros-fp-math when RADV_DEBUG="unsafemath" is usedSamuel Pitoiset2018-01-161-0/+3
| | | | | | | | | | | This is an optimisation that is recommended by Matt Arsenault, and used by RadeonSI, but it's not compatible with Vulkan. Note that AC_FLOAT_MODE_UNSAFE_FP_MATH includes the no signed zeros flag in LLVM. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* ac: set fast math flags when RADV_DEBUG="unsafemath" is usedSamuel Pitoiset2018-01-161-2/+10
| | | | | | | | When that debug option is not used, we use the default float mode because the no signed zeros optimisation is not Vulkan compatible. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* ac: import lp_create_builder() from gallivmSamuel Pitoiset2018-01-162-0/+39
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* ac: replace llvm.AMDGPU.kilp by llvm.amdgcn.kill with LLVM 6Samuel Pitoiset2018-01-161-10/+12
| | | | | | | | This also replaces llvm.AMDGPU.kilp by llvm.AMDGPU.kill with LLVM < 6. Similar to RadeonSI codepath. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* Revert "ac/shader: gather If TES reads TESSINNER or TESSOUTER"Samuel Pitoiset2018-01-155-8/+4
| | | | | | | | | | | | | This can't work for two reasons: - TESSINNER/TESSOUTER are shader input values, so never translated to the intrinsic ops - the shader info pass scans the current stage but we want to know in TCS, if TES reads the tess factors. This fixes 6 regressions related to deqp-vk/tessellation/shader_input_output/tess_level_{inner,outer}_XXX_tes This reverts commit 5ba1a61648e2dea96f621a5886ad8b937a471ab4.
* amd/common: fix loading InstanceID for tess on < GFX9Samuel Pitoiset2018-01-151-2/+1
| | | | | | | | | | InstanceID is in VGPR2, not 1. One more failure that CTS didn't catch up... Reported-by: Alex Smith <[email protected]> Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* ac/shader: gather If TES reads TESSINNER or TESSOUTERSamuel Pitoiset2018-01-155-4/+8
| | | | | | | This shouldn't be scanned in the pipeline. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* ac: remove ac_shader_variant_info::fs::output_maskSamuel Pitoiset2018-01-152-3/+0
| | | | | | | Unused. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* ac: add doubles support to isignTimothy Arceri2018-01-141-7/+18
| | | | | | | | Fixes a number of int64 piglit tests, for example: generated_tests/spec/arb_gpu_shader_int64/execution/built-in-functions/fs-sign-i64vec2.shader_test Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* ac: add i64_0 and i64_1 to llvm build contextTimothy Arceri2018-01-142-0/+4
| | | | | | These will be used in the following patch. Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* ac/nir: fix translation of nir_op_b2i for doublesTimothy Arceri2018-01-141-3/+9
| | | | | | | | | | V2: just zero-extend the 32-bit value. Fixes a number of int64 piglet tests, for example: generated_tests/spec/arb_gpu_shader_int64/execution/conversion/frag-conversion-explicit-bool-int64_t.shader_test Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv/radeonsi/nir: lower 64bit flrpTimothy Arceri2018-01-131-0/+1
| | | | | | | | Fixes a bunch of arb_gpu_shader_fp64 piglit tests for example: generated_tests/spec/arb_gpu_shader_fp64/execution/built-in-functions/fs-mix-double-double-double.shader_test Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* ac: add 'const' qualifiers to the shader info passSamuel Pitoiset2018-01-122-8/+11
| | | | | | | For clarification purposes. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* ac: remove unused ac_nir_compiler_options from gather_info_input_decl()Samuel Pitoiset2018-01-121-4/+2
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: don't emit unneeded vertex state.Dave Airlie2018-01-122-8/+49
| | | | | | | | | | | | | | | | | | If the number of instances hasn't changed and we've already emitted it, don't emit it again. If the vertex shader is the same and the first_instance, vertex_offset haven't changed don't emit them again. This increases the fps in GL_vs_VK -t 1 -m -api vk from around 40 to around 60 here, it may not impact anything else. Dieter also reported smoketest going from 1060->1200 fps. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]> Tested-by: Dieter Nützel <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: trim buffer load result (fixes dota2)Dave Airlie2018-01-121-1/+1
| | | | | | | | | | | Running dota2 since the below commit crashes with an llvm assert. Trim the vector like the other user. This possible could also be avoided by not padding inside the load vec3->vec4. Fixes: 41c36c4549 (amd/common: use ac_build_buffer_load() for emitting UBO loads) Reviewed-by: Samuel Pitoiset <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* meson: Use dependencies for nirDylan Baker2018-01-112-5/+6
| | | | | | | | | | | | | | | | | This creates two new internal dependencies, idep_nir_headers and idep_nir. The former encapsulates the generation of nir_opcodes.h and nir_builder_opcodes.h and adding src/compiler/nir as an include path. This ensures that any target that needs nir headers will have the includes and that the generated headers will be generated before the target is build. The second, idep_nir, includes the first and additionally links to libnir. This is intended to make it easier to avoid race conditions in the build when using nir, since the number of consumers for libnir and it's headers are quite high. Acked-by: Eric Engestrom <[email protected]> Signed-off-by: Dylan Baker <[email protected]>
* meson: Use include variablesDylan Baker2018-01-111-1/+1
| | | | | | | | These were added after adderlib was mesonified, but it still good to use them instead of open coding them. Acked-by: Eric Engestrom <[email protected]> Signed-off-by: Dylan Baker <[email protected]>
* meson: Use consistent styleDylan Baker2018-01-113-18/+33
| | | | | | | | | | | | | | | | | | | | Currently the meosn build has a mix of two styles: arg : [foo, ... bar], and arg : [ foo, ..., bar, ] For consistency let's pick one. I've picked the later style, which I think is more readable, and is more common in the mesa code base. v2: - fix commit message Acked-by: Eric Engestrom <[email protected]> Signed-off-by: Dylan Baker <[email protected]>
* ac/nir: fix translation of nir_op_fsign for doublesTimothy Arceri2018-01-121-7/+19
| | | | | | | | Without this we end up with the llvm error message: "Both operands to a binary operator are not of the same type!" Reviewed-by: Samuel Pitoiset <[email protected]>
* ac: add f64_0 to the llvm build contextTimothy Arceri2018-01-122-0/+2
| | | | Reviewed-by: Samuel Pitoiset <[email protected]>
* ac/nir: fix translation of nir_op_frcp for doublesTimothy Arceri2018-01-121-1/+2
| | | | | | | | Without this we end up with the llvm error message: "Both operands to a binary operator are not of the same type!" Reviewed-by: Samuel Pitoiset <[email protected]>
* ac/nir: fix translation of nir_op_frsq for doublesTimothy Arceri2018-01-121-1/+2
| | | | | | | | Without this we end up with the llvm error message: "Both operands to a binary operator are not of the same type!" Reviewed-by: Samuel Pitoiset <[email protected]>
* ac: add f64_1 to the llvm build contextTimothy Arceri2018-01-122-0/+2
| | | | Reviewed-by: Samuel Pitoiset <[email protected]>
* radv: reset semaphores & fences on sync_file export.Bas Nieuwenhuizen2018-01-111-0/+16
| | | | | | | | | | | | | | | | | | Per spec: "Additionally, exporting a fence payload to a handle with copy transference has the same side effects on the source fence’s payload as executing a fence reset operation. If the fence was using a temporarily imported payload, the fence’s prior permanent payload will be restored." And similar for semaphores: "Additionally, exporting a semaphore payload to a handle with copy transference has the same side effects on the source semaphore’s payload as executing a semaphore wait operation. If the semaphore was using a temporarily imported payload, the semaphore’s prior permanent payload will be restored." Fixes: 42bc25a79c "radv: Advertise sync fd import and export." Reviewed-by: Dave Airlie <[email protected]>
* ac: add load_patch_vertices_in() to the abiTimothy Arceri2018-01-112-1/+12
| | | | | | | | | | | | | Fixes the follow test for radeonsi nir: tests/spec/arb_tessellation_shader/execution/quads.shader_test Also stops 8 other tests from crashing, they now just fail e.g. tcs-output-array-float-index-rd-after-barrier.shader_test Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* ac/nir: Sanitize location_frac for local variables.Bas Nieuwenhuizen2018-01-111-0/+1
| | | | | | | | If they were promoted from inputs/outputs, they could have a non-zero value left over, which messed with our store handling. Fixes: 06f05040eb "radv: Link shaders." Reviewed-by: Timothy Arceri <[email protected]>
* amd/common: use ac_build_buffer_load() for emitting UBO loadsSamuel Pitoiset2018-01-101-14/+3
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* amd/common: import get_{load,store}_intr_attribs() from RadeonSISamuel Pitoiset2018-01-102-10/+20
| | | | | | | v2: move those helpers to the header and use static inline Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> (v1)
* radv: Remove some typos.Bas Nieuwenhuizen2018-01-102-4/+4
| | | | Trivial.
* radv: Implement VK_EXT_discard_rectangles.Bas Nieuwenhuizen2018-01-105-6/+110
| | | | | | | | Tested with a modified deferred demo and no regressions in a 1.0.2 mustpass run. Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: Add mapping between dynamic state mask and external enum.Bas Nieuwenhuizen2018-01-103-38/+79
| | | | | | | | | The EXT values are really large, e.g. VK_DYNAMIC_STATE_DISCARD_RECTANGLE_EXT = 1000099000, so 1 << value is not going to fit into a 32-bit mask. Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* amd/common: bump the number of available user SGPRS to 32 on GFX9Samuel Pitoiset2018-01-101-1/+3
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: remove radv_pipeline_layout::push_constant_stages fieldSamuel Pitoiset2018-01-102-3/+0
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* amd/common: do not rely on the pipeline for the push constants logicSamuel Pitoiset2018-01-103-9/+9
| | | | | | | | It makes more sense to rely on nir_intrinsic_load_push_constant instead of the pipeline layout. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv/gfx9: calculate the number of ES VGPRs for merged shadersSamuel Pitoiset2018-01-101-3/+10
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv/gfx9: enable LDS for GS only if the ES type is TESSamuel Pitoiset2018-01-101-1/+2
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* amd/common: determine the ES type (VS or TES) for the GS on GFX9Samuel Pitoiset2018-01-102-0/+9
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* ac: rework emit_barrier() to not segfault on radeonsiTimothy Arceri2018-01-091-9/+8
| | | | | | | | nir_to_llvm_context will always be NULL for radeonsi so we need work around this. Reviewed-by: Dave Airlie <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* ac: add load_tess_level() to the abiTimothy Arceri2018-01-092-0/+10
| | | | | | | | | | | | | | | | Fixes the following piglit tests in radeonsi: vs-tcs-tes-tessinner-tessouter-inputs-quads.shader_test vs-tcs-tes-tessinner-tessouter-inputs-tris.shader_test vs-tes-tessinner-tessouter-inputs-quads.shader_test vs-tes-tessinner-tessouter-inputs-tris.shader_test v2: make use of si_shader_io_get_unique_index_patch() via the helper in the previous patch rather than shader_io_get_unique_index() Reviewed-by: Nicolai Hähnle <[email protected]> (v1) Reviewed-by: Marek Olšák <[email protected]>
* radv: get InstanceID from VGPR1 (or VGPR2 for tess) instead of VGPR3Samuel Pitoiset2018-01-081-8/+24
| | | | | | | | | VGPR1 = InstanceID / StepRate0; // StepRate0 can be set to 1 Ported from RadeonSI. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: avoid PS partial flushes when viewports/scissors don't changeSamuel Pitoiset2018-01-081-6/+33
| | | | | | | | | | | | | For Vega10 and Raven that need a special workaround for the scissor bug. This seems to give a minor boost for Talos and Dota 2, at least. To reduce the cost of memcmp, the driver checks if it's really useful to do the comparison. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: add has_scissor_bug for Vega10 and RavenSamuel Pitoiset2018-01-083-2/+6
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-14 03:04:27 +0000