summaryrefslogtreecommitdiffstats
path: root/src/amd
Commit message (Collapse)AuthorAgeFilesLines
* amd/addrlib: add Addr2IsValidDisplaySwizzleModeMarek Olšák2017-10-124-2/+58
| | | | | | | | Some "standard" (_S) swizzle modes are displayable on Raven, even though the micro tile mode says it's not displayable. Expose the addrlib function to the driver. Reviewed-by: Nicolai Hähnle <[email protected]>
* radv: don't crash if cache is disabled.Dave Airlie2017-10-121-5/+9
| | | | | | | | If you set MESA_GLSL_CACHE_DISABLE, radv crashed. Fixes: fd24be134f (radv: make use of on-disk cache) Signed-off-by: Dave Airlie <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* radv: use CLEAR_STATE for initializing some registersSamuel Pitoiset2017-10-121-41/+58
| | | | | | | | | Based on RadeonSI. This improves some Vulkan demos by +1% to +3%. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: add has_clear_state and enable it on CIK+ onlySamuel Pitoiset2017-10-122-1/+6
| | | | | | | | This will allow us to emit the CLEAR_STATE packet instead of a bunch of useless packets when doing CS initialization. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: do not set registers for merged ES-GS on GFX9Samuel Pitoiset2017-10-121-2/+5
| | | | | | | Based on RadeonSI. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: move the raster config emission in si_set_raster_config()Samuel Pitoiset2017-10-121-53/+60
| | | | | | | Similar to RadeonSI, also only call this function for <= VI. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: remove duplicate line of codeTimothy Arceri2017-10-121-1/+0
| | | | | | | The same line of code is a few lines above. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* radv: make use of on-disk cacheTimothy Arceri2017-10-121-2/+25
| | | | | | | | If the app provided in-memory pipeline cache doesn't yet contain what we are looking for, or it doesn't provide one at all then we fallback to the on-disk cache. Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: create on-disk shader cacheTimothy Arceri2017-10-122-0/+19
| | | | | | | This is the drivers on-disk cache intended to be used as a fallback as opposed to the pipeline cache provided by apps. Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: remove duplicate debug_flags fieldTimothy Arceri2017-10-129-17/+14
| | | | | Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: Only set the MTYPE flags on GFX9+.Bas Nieuwenhuizen2017-10-111-1/+1
| | | | | | | | Older kernels fail the va_op with this flag set. If the kernel supports GFX9 usefully, it will also support this flag. Fixes: e8d57802fea "radv/gfx9: allocate events from uncached VA space" Reviewed-by: Dave Airlie <[email protected]>
* radv: lower ffma in nir.Dave Airlie2017-10-111-0/+1
| | | | | | | | | | | | | | | | | So it appears the Vulkan SPIR-V fma opcode can be equivalent to a mad operation, and the fma hw opcode on AMD hw is issued like a double opcode so is slower. Also the radeonsi stack does this. This appears to improve performance on a number of games from Feral, and thanks to Feral for noticing the problem. I'm reposting this one as Marek indicated he thinks this is what we should be doing on AMD hw. Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Cc: "17.2" <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: Add R16G16B16A16_SNORM fast clear supportAlex Smith2017-10-111-0/+6
| | | | | | Signed-off-by: Alex Smith <[email protected]> Cc: "17.2" <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: export KHR_relaxed_block_layoutDave Airlie2017-10-101-0/+4
| | | | | | | | This seems to pass all the cts tests it enables. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Acked-by: Jason Ekstrand <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* amd: move r600d_common.h into r600gMarek Olšák2017-10-099-163/+23
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: shrink r600d_common.h and stop using itMarek Olšák2017-10-095-185/+37
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radv: configure VGT_VERTEX_REUSE at pipeline creationSamuel Pitoiset2017-10-093-10/+16
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: do not need to zero-init ds/raster statesSamuel Pitoiset2017-10-091-3/+0
| | | | | | | Already done when creating the pipeline. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: remove unused fields in radv_raster_stateSamuel Pitoiset2017-10-091-3/+0
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: set ALPHA_TO_MASK_ENABLE at blend state initSamuel Pitoiset2017-10-091-7/+7
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: emit PA_SU_POINT_{SIZE,MINMAX} in si_emit_config()Samuel Pitoiset2017-10-092-16/+15
| | | | | | | | | These registers don't change during the lifetime of the command buffer, there is no need to re-emit them when binding a new pipeline. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: allow launching waves out-of-order for computeSamuel Pitoiset2017-10-091-1/+9
| | | | | | | | Ported from RadeonSI, and -pro seems to enable it as well. Signed-off-by: Samuel Pitoiset <[email protected]> Acked-by: Nicolai Hähnle <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: convert all COMPUTE operations to the RADV_META_SAVE_XXX flagsSamuel Pitoiset2017-10-067-107/+62
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: add RADV_META_SAVE_COMPUTE_PIPELINE flagSamuel Pitoiset2017-10-062-2/+23
| | | | | | | This will allow use to merge the compute save/restore helpers. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: add radv_meta_save() helperSamuel Pitoiset2017-10-069-73/+58
| | | | | | | | And merge radv_meta_save_novertex() with radv_meta_save_graphics_reset_vport_scissor_novertex(). Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: merge radv_meta_{save,restore}_pass() with RADV_META_SAVE_PASSSamuel Pitoiset2017-10-064-39/+22
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: convert all GFX operations to the RADV_META_SAVE_XXX flagsSamuel Pitoiset2017-10-067-13/+46
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: introduce the concept of meta save flagsSamuel Pitoiset2017-10-069-52/+85
| | | | | | | | | | | This will allow us to save/restore the different states on-demand based on the meta operation. For now, this saves/restores all states. Compute will follow once the graphics part is done. The main idea is to merge all save/restore helpers. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: remove unused RADV_META_VERTEX_BINDING_COUNTSamuel Pitoiset2017-10-061-2/+0
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: select the pipeline outside of the loop when decompressing htileSamuel Pitoiset2017-10-061-12/+12
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: add radv_htile_enabled() helperSamuel Pitoiset2017-10-062-3/+8
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* ac: properly document a buffer.store LLVM workaroundMarek Olšák2017-10-062-6/+9
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radv: Enable VK_KHR_maintenance2 extension.Bas Nieuwenhuizen2017-10-062-0/+5
| | | | Reviewed-by: Dave Airlie <[email protected]>
* radv: Make tess winding order a bit more intuitive.Bas Nieuwenhuizen2017-10-061-3/+2
| | | | Reviewed-by: Dave Airlie <[email protected]>
* radv: Allow setting the domain origin in tess.Bas Nieuwenhuizen2017-10-061-1/+9
| | | | Reviewed-by: Dave Airlie <[email protected]>
* radv: Disable usage checks in metadata for images with extended usage data.Bas Nieuwenhuizen2017-10-061-1/+3
| | | | | | | The app can extend the usage, so knowing that the usage is limitied does not help us here. Reviewed-by: Dave Airlie <[email protected]>
* radv: Implement querying the point clipping behavior.Bas Nieuwenhuizen2017-10-061-0/+6
| | | | Reviewed-by: Dave Airlie <[email protected]>
* meson: generate builddir/src/amd/vulkan/dev_icd.jsonBas Nieuwenhuizen2017-10-053-2/+9
| | | | Reviewed-by: Dylan Baker <[email protected]>
* radv: remove useless checks around radv_CmdBindPipeline()Samuel Pitoiset2017-10-048-97/+34
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: check that pipeline is different before binding itSamuel Pitoiset2017-10-041-2/+8
| | | | | | | | We only need to dirty the descriptors when the pipeline is a new one, because user SGPRs can be potentially different. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: enable tc compatible htile for d32s8 also.Dave Airlie2017-10-041-1/+2
| | | | | | | | | | | | This enables tc compatible htile for stencil surfaces as well. This gives a 3-5fps boost on Mad Max on high@4k. It also depends on Bas's tc-compat htile patch. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: dump SPIRV when a GPU hang is detectedSamuel Pitoiset2017-10-044-4/+13
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: dump NIR when a GPU hang is detectedSamuel Pitoiset2017-10-044-11/+27
| | | | | | | | This looks a bit ugly to me, but the existing codepath is not terribly elegant as well. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* ac: silence a warningMarek Olšák2017-10-041-1/+3
|
* radv: Implement TC compatible HTILE.Bas Nieuwenhuizen2017-10-044-6/+62
| | | | | | | The situations where we enable it are quite limitied, but it works, even for madmax, so lets just enable it. Reviewed-by: Dave Airlie <[email protected]>
* radv: emit fmuladd instead of fma to llvm.Dave Airlie2017-10-041-1/+1
| | | | | | | | | | | | | | | | | | | | For Vulkan SPIR-V the spec states fma() Inherited from OpFMul followed by OpFAdd. Matt says the backend will do the right thing depending on the hardware being compiled for, if you use the fmuladd intrinsic. Using the Mad Max pts test, on high settings at 4K: CHP: 55->60 HGDD: 46->50 LM: 55->60 No change on Stronghold. Thanks to Feral for spending the time to track this down. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Cc: "17.2" <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: make radv_dynamic_state_copy() staticSamuel Pitoiset2017-10-022-5/+1
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* amd/common: move ac_build_phi from radeonsiNicolai Hähnle2017-10-022-0/+19
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radv: remove unused radv_meta_state::btoi::render_pass handleSamuel Pitoiset2017-10-021-1/+0
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: do not check the number of levels when doing fast htileSamuel Pitoiset2017-10-021-3/+0
| | | | | | | | We shouldn't reach this point because HTILE is only enabled when the number of levels is 1. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-22 11:41:17 +0000