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* radv: Disable texel buffers with A2 SNORM/SSCALED/SINT for pre-vega.Bas Nieuwenhuizen2018-05-151-0/+19
| | | | | | | | | | The hardware always interprets the alpha as unsigned and fixing it in the shader is going to add unacceptable overheads. CC: 18.0 18.1 <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106480 Reviewed-by: Samuel Pitoiset <[email protected]> (cherry picked from commit f944a59996287de85d4c6d9b7b000d25f41b1d79)
* radv: Fix up 2_10_10_10 alpha sign.Bas Nieuwenhuizen2018-05-154-11/+98
| | | | | | | | | | | | | Pre-Vega HW always interprets the alpha for this format as unsigned, so we have to implement a fixup to do the sign correctly for signed formats. v2: Improve indexing mess. CC: 18.0 <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106480 Reviewed-by: Samuel Pitoiset <[email protected]> (Backport of 3d4d388e392 "radv: Fix up 2_10_10_10 alpha sign.")
* radv: Translate logic ops.Bas Nieuwenhuizen2018-05-152-30/+59
| | | | | | | | | | | | | | | | | radeonsi could pass them through but the enum changed between Gallium and Vulkan, so we have to translate. In progress I made the register defines a bit more readable. CC: 18.0 18.1 <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100430 Reviewed-by: Samuel Pitoiset <[email protected]> (cherry picked from commit dd102405dea022f6c27bc42176f50f3bb2761ae6) [Juan A. Suarez: resolve trivial conflicts] Signed-off-by: Juan A. Suarez Romero <[email protected]> Conflicts: src/amd/vulkan/radv_pipeline.c
* radv: use compute path for multi-layer images.Dave Airlie2018-05-151-0/+2
| | | | | | | | | | | | I don't think the hw resolve path can't handle multi-layer images. This fixes all the: dEQP-VK.renderpass.multisample_resolve.layers_* tests on my VI card. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Cc: <[email protected]> (cherry picked from commit 5978d54a09e6ad151c0bd365de0e2c82bbf493d1)
* radv: resolve all layers in compute resolve path.Dave Airlie2018-05-151-6/+42
| | | | | | | | | | | | This path should iterate across all layers, I've some ideas for doing this in a single pass, but this is simpler for now. This passes the tests because we don't use the fragment path unless we have DCC, and we don't have DCC on layered images. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Cc: <[email protected]> (cherry picked from commit 98dbaa445a83108b59bd56e8f3224c13c36ba1d5)
* radv: fix multisample image copiesMatthew Nicholls2018-05-072-110/+196
| | | | | | | | | | | | | | | | | | | | Previously before fb077b0728, the LOD parameter was being used in place of the sample index, which would only copy the first sample to all samples in the destination image. After that multisample image copies wouldn't copy anything from my observations. This fixes some copy_and_blit CTS tests. v3.1: - set lod to 0 for nir_txf_ms (Samuel) v2: - use GLSL_SAMPLER_DIM_MS instead of 2D (Samuel) - updated commit description (Samuel) Fix this properly by copying each sample in a separate radv_CmdDraw and using a pipeline with the correct rasterizationSamples for the destination image. Cc: 18.0 18.1 <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> (cherry picked from commit 97d57ef9174111bfe1fa6f85e022af5a3cf2f1ce)
* radv: compute the number of subpass attachments correctlySamuel Pitoiset2018-05-021-2/+2
| | | | | | | | | | Only count color attachments twice if resolves are used, also account for the depth stencil attachment if present. Cc: 18.0 18.1 <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Samuel Pitoiset <[email protected]> (cherry picked from commit d8db5986cee83078e46895d695d698db87507019)
* radv/winsys: fix leaking resources from bo's imported by fdAndres Rodriguez2018-05-021-0/+1
| | | | | | | | | | | | | A bo's ref_count was not being initialized when imported from an fd. Therefore, we would fail to free the resource during VkFreeMemory(). This patch fixes applications like hifi VR in threaded mode, which perform frequent imports/releases of IPC shared memory. Signed-off-by: Andres Rodriguez <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> CC: 18.0 18.1 <[email protected]> (cherry picked from commit f56e22e49673e8234a7fe0c241b4c3eae4752f34)
* radv/winsys: allow to submit up to 4 IBs for chips without chainingSamuel Pitoiset2018-04-251-50/+169
| | | | | | | | | | | | | | | | | | | The SI family doesn't support chaining which means the maximum size in dwords per CS is limited. When that limit was reached we failed to submit the CS and the application crashed. This patch allows to submit up to 4 IBs which is currently the limit, but recent amdgpu supports more than that. Please note that we can reach the limit of 4 IBs per submit but currently we can't improve that. The only solution is to upgrade libdrm. That will be improved later but for now this should fix crashes on SI or when using RADV_DEBUG=noibs. Fixes: 36cb5508e89 ("radv/winsys: Fail early on overgrown cs.") Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105775 Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Samuel Pitoiset <[email protected]>
* radv: Mark GTT memory as device local for APUs.Bas Nieuwenhuizen2018-04-231-3/+5
| | | | | | | | | Otherwise a lot of games complain about not having enough memory, and it is sort of local so this seems reasonable to me. CC: 18.0 <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]> (cherry picked from commit e1df849c3cfe0c9da7d2f62fc78be94632949903)
* radv: fix scissor computation when using half-pixel viewport offsetSamuel Pitoiset2018-04-231-4/+4
| | | | | | | | | | | | 'scale[i]' can be non-integer. Original patch by Philip Rebohle. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106074 Fixes: 0f3de89a56a ("radv: Use the guard band.") Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Niuwenhuizen <[email protected]> (cherry picked from commit 893e19efb74edd6133a607e09338bf5d449632f1)
* ac/nir: Make the GFX9 buffer size fix apply to image loads/atomics too.Bas Nieuwenhuizen2018-04-231-17/+22
| | | | | | | | | | | | | | | No clue how I missed those ... Fixes: 4503ff760c "ac/nir: Add workaround for GFX9 buffer views." CC: <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105320 Reviewed-by: Nicolai Hähnle <[email protected]> (cherry picked from commit b0e3a9b19f16ed1ce4c1f150718b0c0f0e6111f6) [Juan A. Suarez: resolve trivial conflicts] Signed-off-by: Juan A. Suarez Romero <[email protected]> Conflicts: src/amd/common/ac_nir_to_llvm.c
* radv: fix radv_layout_dcc_compressed() when image doesn't have DCCSamuel Pitoiset2018-04-121-1/+1
| | | | | | | | | | | | | | | | | | | num_dcc_levels means that DCC is supported, but this doesn't mean that it's enabled by the driver. Instead, we should rely on radv_image_has_dcc(). This fixes some multisample regressions since 0babc8e5d66 ("radv: fix picking the method for resolve subpass") on Vega. This is because the resolve method changed from HW to FS, but those fails are totally unexpected, so there might some differences between Polaris and Vega here. Fixes: 44fcf587445 ("radv: Disable DCC for GENERAL layout and compute transfer dest.") Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> (cherry picked from commit 9eac49246cdc501530418e8bd2a3e6d47173332b) [Juan A. Suarez: do not call radv_image_has_dcc(), as it is not defined] Signed-off-by: Juan A. Suarez Romero <[email protected]>
* radv: fix picking the method for resolve subpassSamuel Pitoiset2018-04-121-1/+1
| | | | | | | | | | | | The source and destination image parameters were swapped. No CTS changes on Polaris10, but I suspect this might fix something. Fixes: 2a04f5481df ("radv/meta: select resolve paths") Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> (cherry picked from commit 0babc8e5d665e54783c926b89183ab9a596aa04c)
* radv: Always reset draw user SGPRs after secondary command buffer.Bas Nieuwenhuizen2018-04-121-14/+3
| | | | | | | | | As we sometimes reset them to -1, -1 does not mean that they are not written by the secondary command buffer. Fixes: ad11fc3571 "radv: don't emit unneeded vertex state." Reviewed-by: Samuel Pitoiset <[email protected]> (cherry picked from commit 41fbcc7901bc7a95fb7d5ccffdb3c18ba0361c40)
* radv: Don't set instance count using predication.Bas Nieuwenhuizen2018-04-121-1/+1
| | | | | | | | | | | The packet can sometimes be skipped, but we still think the change takes effect. This just makes the packet always take effect. Fixes: ad11fc3571 "radv: don't emit unneeded vertex state." Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105942 Reviewed-by: Samuel Pitoiset <[email protected]> (cherry picked from commit 74b0b869ddd4dbd36482aa9bec3403d45396af2d)
* ac/nir: Add workaround for GFX9 buffer views.Bas Nieuwenhuizen2018-04-124-6/+62
| | | | | | | | | | | | | | | | | | | | | | | | | | | | On GFX9 whether the buffer size is interpreted as elements or bytes depends on whether IDXEN is enabled in the instruction. If the index is a constant zero, LLVM optimizes IDXEN to 0. Now the size in elements is interpreted in bytes which of course results in out of bounds accesses. The correct fix is most likely to disable the LLVM optimization, but we need something to work with LLVM <= 6.0. radeonsi does the max between stride and element count on the CPU but that results in the size intrinsics returning the wrong size for the buffer. This would cause CTS errors for radv. v2: Also include the store changes. Fixes: e38685cc62e 'Revert "radv: disable support for VEGA for now."' Reviewed-by: Samuel Pitoiset <[email protected]> (cherry picked from commit 4503ff760c794c3bb15b978a47c530037d56498e) [Juan A. Suarez: partially backported from 908a0cd1dbe5, a backport for 17.3 stable branch; resolved trivial conflicts] Conflicts: src/amd/common/ac_nir_to_llvm.c src/amd/vulkan/radv_nir_to_llvm.c
* ac: make use of if/loop build helpersTimothy Arceri2018-04-121-42/+18
| | | | | | | | | | | | | These helpers insert the basic block in the same order as they appear in NIR making it easier to follow LLVM IR dumps. The helpers also insert more useful labels onto the blocks. TGSI use the line number of the corresponding opcode in the TGSI dump as the label id, here we use the corresponding block index from NIR. Reviewed-by: Marek Olšák <[email protected]> (cherry picked from commit 99cdc019bf6fe11c135b7544ef6daf4ac964fa24)
* ac: add if/loop build helpersTimothy Arceri2018-04-123-0/+212
| | | | | | | | | | | | | These have been ported over from radeonsi. Reviewed-by: Marek Olšák <[email protected]> (cherry picked from commit 42627dabb4db3011825a022325be7ae9b51103d6) [Juan A. Suarez: resolve trivial conflicts] Signed-off-by: Juan A. Suarez Romero <[email protected]> Conflicts: src/amd/common/ac_llvm_build.c src/amd/common/ac_llvm_build.h
* radv: mark all tess output for an indirect access.Dave Airlie2018-03-201-8/+13
| | | | | | | | | | | | | | | | | If a shader does a tcs store with an indirect access, we were only marking the first spot as used. For indirect access we always now mark all slots used by the variable. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105464 Fixes: 94f9591995 (radv/ac: add support for TCS/TES inputs/outputs.) Signed-off-by: Dave Airlie <[email protected]> (cherry picked from commit 27a5e5366e89498d98d786cc84fafbdb220c4d94) Emil Velikov: move hunks {radv,ac}_nir_to_llvm.c] Signed-off-by: Emil Velikov <[email protected]> Conflicts: src/amd/vulkan/radv_nir_to_llvm.c
* ac/nir: pass the nir variable through tcs loading.Dave Airlie2018-03-202-17/+11
| | | | | | | | | | | | | | | | | | | | I was going to have to add another parameter to this monster, so we should just pass the nir_variable in, I can't find any reason this would be a bad idea. This needed for the next fix. Fixes: 94f9591995 (radv/ac: add support for TCS/TES inputs/outputs.) Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]> (cherry picked from commit 4f0c89d66c570e82d832e2e49227517302e271a2) [Emil Velikov: move hunk {radv,ac}_nir_to_llvm.c] Signed-off-by: Emil Velikov <[email protected]> Conflicts: src/amd/common/ac_nir_to_llvm.c src/amd/common/ac_shader_abi.h src/amd/vulkan/radv_nir_to_llvm.c
* radv: get correct offset into LDS for indexed vars.Dave Airlie2018-03-201-1/+1
| | | | | | | | | | | | | | | | | | This seems more correct to me, since if we have an array of floats they'll be vec4 aligned, and if we do af[2], we want the const index to increase by 2 slots in the non compact case. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105464 Fixes: 94f9591995 (radv/ac: add support for TCS/TES inputs/outputs.) Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]> (cherry picked from commit f9de2d409bf4f068a99d358d592d96ab4803f7fb) [Emil Velikov: hunk belongs to another file {radv,ac}_nir_to_llvm.c] Signed-off-by: Emil Velikov <[email protected]> Conflicts: src/amd/vulkan/radv_nir_to_llvm.c
* radv: Fix copying from 3D images starting at non-zero depth.Bas Nieuwenhuizen2018-03-201-0/+3
| | | | | | Fixes: f4e499ec79 "radv: add initial non-conformant radv vulkan driver" Reviewed-by: Dave Airlie <[email protected]> (cherry picked from commit eea20d59abd304953c8c1591612d45d3d94eb785)
* radv: Implement waiting on non-submitted fences.Bas Nieuwenhuizen2018-03-201-2/+11
| | | | | | Fixes: f4e499ec79 "radv: add initial non-conformant radv vulkan driver" Reviewed-by: Dave Airlie <[email protected]> (cherry picked from commit 6968d782d3063c639e80dbcf6df944902d72692f)
* radv: Implement WaitForFences with !waitAll.Bas Nieuwenhuizen2018-03-201-5/+15
| | | | | | | | | | | Nothing to do except using a busy wait loop. At least for old kernels. A better implementation for newer kernels to come later. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105255 Fixes: f4e499ec79 "radv: add initial non-conformant radv vulkan driver" Reviewed-by: Dave Airlie <[email protected]> (cherry picked from commit 2a404c6f923880cfd0bc04f9db1890cadce8bd92)
* ac/nir: don't apply slice rounding on txf_msDave Airlie2018-03-201-1/+1
| | | | | | | | | | | | | | | | | This matches the tgsi code. Fixes arb_texture_multisample texelFetch piglit tests. Reviewed-by: Timothy Arceri <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Fixes: f4e499ec7914 (radv: add initial non-conformant radv vulkan driver) Signed-off-by: Dave Airlie <[email protected]> (cherry picked from commit 69495b30a38fbb01a937cdea6f7674f89a2e60e7) [Emil Velikov: trivial conflicts] Signed-off-by: Emil Velikov <[email protected]> Conflicts: src/amd/common/ac_nir_to_llvm.c
* radv: do not set pending_reset_query in BeginCommandBuffer()Samuel Pitoiset2018-03-201-7/+0
| | | | | | | | | | | | | | This is just useless for two reasons: 1) flush_bits is not set accordingly, so nothing will be flushed in BeginQuery(). 2) we always flush caches in EndCommandBuffer(), so if a reset is done in a previous command buffer we are safe. Cc: "18.0" <[email protected]> Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Alex Smith <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> (cherry picked from commit c133a3411bbf47c2ba7d9cdae7e35a64fe276068)
* radv: Fix CmdCopyImage between uncompressed and compressed imagesAlex Smith2018-03-201-6/+17
| | | | | | | | | | | | | | | | | | From the spec: "When copying between compressed and uncompressed formats the extent members represent the texel dimensions of the source image and not the destination." However, as per 7b890a36, we must still use the destination image type when clamping the extent so that we copy the correct number of layers for 2D to 3D copies. Fixes: 7b890a36 "radv: Fix vkCmdCopyImage for 2d slices into 3d Images" Cc: <[email protected]> Signed-off-by: Alex Smith <[email protected]> Reviewed-by: Dave Airlie <[email protected]> (cherry picked from commit fcf267ba087dd00c48ceaf9277424dac079f9319)
* radv: Increase the number of dynamic uniform buffers.Bas Nieuwenhuizen2018-03-202-3/+5
| | | | | | | | | | | | | | The vulkan API is not ideal as it does not allow us have a shared limit. Feral needs 15+6 for one of their games, and I'm not a fan of overcommitting the limits, so increase the number of dynamic uniform buffers to 16. CC: <[email protected]> CC: Alex Smith <[email protected]> Reviewed-by: Dave Airlie <[email protected]> (cherry picked from commit 997306c031327b7e034e617736c868d6d21919eb)
* radeonsi: align command buffer starting address to fix some Raven hangsMarek Olšák2018-03-202-1/+20
| | | | | | | | | | | | Cc: 17.3 18.0 <[email protected]> Reviewed-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> (cherry picked from commit 75c5d25f0f34cd70246ee1b0b77a75ec82dfcecb) [Emil Velikov: remove uvd_enc hunk - missing in branch] Signed-off-by: Emil Velikov <[email protected]> Conflicts: src/amd/common/ac_gpu_info.c
* radv: make sure to emit cache flushes before starting a querySamuel Pitoiset2018-03-203-7/+33
| | | | | | | | | | | | If the query pool has been previously resetted using the compute shader path. Fixes: a41e2e9cf5 ("radv: allow to use a compute shader for resetting the query pool") Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105292 Cc: "18.0" <[email protected]> Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> (cherry picked from commit c956d0f4069cf39d8d3c57ebed8d905575e9ea34)
* ac/nir: use ordered float comparisons except for not equalSamuel Pitoiset2018-03-201-3/+3
| | | | | | | | | | | | | | | | | | | Original patch from Timothy Arceri, I have just fixed the not equal case locally. This fixes one important rendering issue in Wolfenstein 2 (the cutscene transition issue). RadeonSI uses the same ordered comparisons, so I guess that what we should do as well. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104302 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104905 Cc: <[email protected]> Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Connor Abbott <[email protected]> (cherry picked from commit e05507a427b79e481eb8e45d7aa3c9b4b78376bf)
* radv: Really use correct HTILE expanded words.James Legg2018-03-201-3/+3
| | | | | | | | | | | | | | | | | | | | | When transitioning to an htile compressed depth format, Set the full depth range, so later rasterization can pass HiZ. Previously, for depth only formats, the depth range was set to 0 to 0. This caused unwanted HiZ rejections with a VK_FORMAT_D16_UNORM depth buffer (VK_FORMAT_D32_SFLOAT was not affected somehow). These values are derived from PAL [0], since I can't find the specification describing the htile values. [0] https://github.com/GPUOpen-Drivers/pal/blob/5cba4ecbda9452773f59692f5915301e7db4a183/src/core/hw/gfxip/gfx9/gfx9MaskRam.cpp#L1500 CC: Dave Airlie <[email protected]> CC: Bas Nieuwenhuizen <[email protected]> CC: [email protected] Reviewed-by: Bas Nieuwenhuizen <[email protected]> Tested-by: Grazvydas Ignotas <[email protected]> Fixes: 5158603182fe7435 "radv: Use correct HTILE expanded words." (cherry picked from commit afd8fd0656a8eb3a2ce892381387aad3c6b0a78f)
* ac/nir: Fix compiler warning about uninitialized dw_addr.Eric Anholt2018-03-201-1/+1
| | | | | | | | | Even switching the def's condition to be the same chip revision check as the use, the compiler doesn't figure it out. Just NULL-init it. Fixes: ec53e527421d ("ac/nir: Add ES output to LDS for GFX9.") Reviewed-by: Bas Nieuwenhuizen <[email protected]> (cherry picked from commit 091bff831721b62243840038f505af0abd9436c1)
* radv: don't support tc-compat on multisample d32s8 at all.Dave Airlie2018-03-201-2/+2
| | | | | | | | | | | | | RX550 fails dEQP-VK.renderpass.suballocation.multisample.d32_sfloat_s8_uint.samples_2 So increase the range of the workaround. Fixes: f4c534ef6 (radv: don't enable tc compat for d32s8 + 4/8 samples (v1.1)) Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]> (cherry picked from commit e7e81f362d6dc4fe3a272cdd07724a26391e8f5e)
* ac/nir: to integer the args to bcsel.Dave Airlie2018-03-201-1/+2
| | | | | | | | | | | | | | dEQP-VK.tessellation.invariance.outer_edge_symmetry.triangles_equal_spacing_ccw was hitting an llvm assert due to one value being an int and the other a float. This just casts both values to integer and fixes the test. Fixes: dEQP-VK.tessellation.invariance.outer_edge_symmetry.triangles_equal_spacing_ccw Cc: [email protected] Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]> (cherry picked from commit d5b2d7ed670e6b6a2d7a96e588cb3de852d0b289)
* radv: Always lower indirect derefs after nir_lower_global_vars_to_local.Bas Nieuwenhuizen2018-02-283-36/+53
| | | | | | | | | Otherwise new local variables can cause hangs on vega. CC: <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105098 Reviewed-by: Timothy Arceri <[email protected]> (cherry picked from commit 05d84ed68add9e6adfcc602a274405e04226c1b7)
* radv: remove predication on cache flushesMatthew Nicholls2018-02-054-18/+13
| | | | | | | | | | | | | | | This can lead to a situation where cache flushes could get conditionally disabled while still clearing the flush_bits, and thus flushes due to application pipeline barriers may never get executed. Fixes: a6c2001ace (radv: add support for cmd predication.) Signed-off-by: Dave Airlie <[email protected]> (cherry picked from commit ef272b161e05e8216f2d1f4df5023f3aed0ae4fa) [Emil Velikov: trivial conflicts] Signed-off-by: Emil Velikov <[email protected]> Conflicts: src/amd/vulkan/radv_cmd_buffer.c
* radv/gfx9: fix block compression texture views. (v2)Dave Airlie2018-02-051-4/+49
| | | | | | | | | | | | | | | | | This ports a fix from amdvlk, to fix the sizing for mip levels when block compressed images are viewed using uncompressed views. My original fix didn't power the clamping, but it looks like the clamping is required to stop the sizing going too large. Fixes: dEQP-VK.image.texel_view_compatible.graphic.extended*bc* Doesn't crash DOW3 anymore. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Fixes: e38685cc62e 'Revert "radv: disable support for VEGA for now."' Signed-off-by: Dave Airlie <[email protected]> (cherry picked from commit f6cc15dccd54ff70be987457af790cac1c8fe5bb)
* radv: Signal fence correctly after sparse binding.Bas Nieuwenhuizen2018-02-051-14/+32
| | | | | | | | | | It did not signal syncobjs in the fence, and also signalled too early if there was work on the queue already, as we have to wait till that work is done. Fixes: d27aaae4d2 "radv: Add external fence support." Reviewed-by: Samuel Pitoiset <[email protected]> (cherry picked from commit 0347a83bbfd8d993742e125335c6ae46a6aa5a15)
* radv: Stop advertising VK_KHX_multiviewEmil Velikov2018-02-051-1/+1
| | | | | | | | We don't want to advertise experimental extensions in actual releases. However, there's no harm in leaving the code lying around in the tree. [Emil Velikov: port from equivalent ANV commit] Signed-off-by: Emil Velikov <[email protected]>
* radv: don't enable tc compat for d32s8 + 4/8 samples (v1.1)Dave Airlie2018-01-261-1/+2
| | | | | | | | | | | | | | | | | | | This seems to be broken, at least the cts tests fail. This fixes: dEQP-VK.renderpass.suballocation.multisample.d32_sfloat_s8_uint.samples_4 dEQP-VK.renderpass.suballocation.multisample.d32_sfloat_s8_uint.samples_8 2 samples seems to pass fine, amdvlk doesn't appear to enable TC for possibly some other reasons here. This is most likely a hack. v1.1: add a bit of explaination text. (Samuel) Fixes: ad3d98da9 (radv: enable tc compatible htile for d32s8 also.) Signed-off-by: Dave Airlie <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]> (cherry picked from commit f4c534ef68a479055190f8ec8d551be0f56ef361)
* radv: move spi_baryc_cntl to pipelineDave Airlie2018-01-263-5/+5
| | | | | | | | | | | | | We need to enable the pos float location 2 mode anytime we have persample not just when forced by the frag shader. This fixes: dEQP-VK.pipeline.multisample.min_sample_shading* Fixes: 58c97a079 (radv: enable location at sample when persample is forced.) Reviewed-by: Samuel Pitoiset <[email protected]> Signed-off-by: Dave Airlie <[email protected]> (cherry picked from commit 298554541da220ebdcd9aa9b9055ede2481d5817)
* radv: fix sample_mask_in loading. (v3.1)Dave Airlie2018-01-264-6/+56
| | | | | | | | | | | | | | | This is ported from radeonsi and fixes: dEQP-VK.pipeline.multisample_shader_builtin.sample_mask.bit_* v2: don't call this path for radeonsi, it does it in the epilog. use the radeonsi code path. v3: handle NULL pCreateInfo->pMultisampleState properly (Samuel) v3.1: set ps_iter_samples default to 1 (Bas) Reviewed-by: Bas Nieuwenhuizen <[email protected]> Fixes: bdcbe7c76 (radv: add sample mask input support) Signed-off-by: Dave Airlie <[email protected]> (cherry picked from commit 766589d89a211e67f313e8cb38f2d05b09975f96)
* radv: don't use hw resolves for r16g16 norm formats.Dave Airlie2018-01-261-1/+4
| | | | | | | | | | | | | | radeonsi has a workaround for this, but it uses a R16A16 format, which vulkan doesn't have, we could probably come up with a work around but for now just avoid hw resolves. Fixes: dEQP-VK.renderpass.suballocation.multisample.r16g16_*norm* Reviewed-by: Bas Nieuwenhuizen <[email protected]> Fixes: 2a04f5481d (radv/meta: select resolve paths) Signed-off-by: Dave Airlie <[email protected]> (cherry picked from commit c727ea9370adc5362e00208b9f1481764b8ef215)
* radv: don't use hw resolve for integer image formatsDave Airlie2018-01-261-0/+5
| | | | | | | | | | | | | | | From reading AMDVLK it currently never uses hw resolve paths. This patch takes from radeonsi which doesn't use hw resolve for integer formats, and does the same for radv. This fixes: dEQP-VK.renderpass.suballocation.multisample*uint tests. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Fixes: 2a04f5481d (radv/meta: select resolve paths) Signed-off-by: Dave Airlie <[email protected]> (cherry picked from commit 4df414bbd2f1a44840c982198f4c8353f242ca15)
* radv: add fs_key meta format support to resolve passes.Dave Airlie2018-01-262-30/+61
| | | | | | | | | | | | | Some of the hw resolve passes need the SPI color format setup correctly. This fixes lots of 16-bit and 32-bit format tests in dEQP-VK.renderpass.suballocation.multisample* Reviewed-by: Bas Nieuwenhuizen <[email protected]> Fixes: f4e499ec7914 "radv: add initial non-conformant radv vulkan driver" Signed-off-by: Dave Airlie <[email protected]> (cherry picked from commit 316d762186f0bfc225b82794fdae520275a448db)
* ac/nir: set amdgpu.uniform and invariant.load for UBOsSamuel Pitoiset2018-01-261-1/+7
| | | | | | | | | | | UBOs are constants buffers. Cc: "18.0" <[email protected]> Fixes: 41c36c45 ("amd/common: use ac_build_buffer_load() for emitting UBO loads") Signed-off-by: Samuel Pitoiset <[email protected]> Tested-by: Alex Smith <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> (cherry picked from commit 49b0a140a731069e0e4959c65bfd1b597a4fb141)
* ac/nir: Use instance_rate_inputs per attribute, not per variable.Bas Nieuwenhuizen2018-01-231-14/+13
| | | | | | | | | | This did the wrong thing if we had e.g. an array for which only some of the attributes use the instance index. Tripped up some new CTS tests. CC: <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* ac: fix image load store for GLSL_SAMPLER_DIM_3DTimothy Arceri2018-01-231-1/+3
| | | | | | | | | | | | Fixes the following piglit tests: arb_shader_image_load_store/layer/image3d/layered binding test arb_shader_image_load_store/max-size/image3d max size test/2048x8x8x1 arb_shader_image_load_store/max-size/image3d max size test/8x2048x8x1 arb_shader_image_load_store/max-size/image3d max size test/8x8x2048x1 arb_shader_image_load_store/semantics/imageload/vertex shader/rgba32f/image3d test Reviewed-by: Nicolai Hähnle <[email protected]>
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