summaryrefslogtreecommitdiffstats
path: root/src/amd
Commit message (Expand)AuthorAgeFilesLines
* amd/common: bump the number of available user SGPRS to 32 on GFX9Samuel Pitoiset2018-01-101-1/+3
* radv: remove radv_pipeline_layout::push_constant_stages fieldSamuel Pitoiset2018-01-102-3/+0
* amd/common: do not rely on the pipeline for the push constants logicSamuel Pitoiset2018-01-103-9/+9
* radv/gfx9: calculate the number of ES VGPRs for merged shadersSamuel Pitoiset2018-01-101-3/+10
* radv/gfx9: enable LDS for GS only if the ES type is TESSamuel Pitoiset2018-01-101-1/+2
* amd/common: determine the ES type (VS or TES) for the GS on GFX9Samuel Pitoiset2018-01-102-0/+9
* ac: rework emit_barrier() to not segfault on radeonsiTimothy Arceri2018-01-091-9/+8
* ac: add load_tess_level() to the abiTimothy Arceri2018-01-092-0/+10
* radv: get InstanceID from VGPR1 (or VGPR2 for tess) instead of VGPR3Samuel Pitoiset2018-01-081-8/+24
* radv: avoid PS partial flushes when viewports/scissors don't changeSamuel Pitoiset2018-01-081-6/+33
* radv: add has_scissor_bug for Vega10 and RavenSamuel Pitoiset2018-01-083-2/+6
* radv/gfx9: do not load VGPR1 when GS uses points or linesSamuel Pitoiset2018-01-081-1/+3
* radv: make shader BOs read-only for the GPUSamuel Pitoiset2018-01-083-1/+7
* radv: make descriptor BOs read-only for the GPUSamuel Pitoiset2018-01-082-3/+7
* radv: make the indirect GFX config BO read-only for the GPUSamuel Pitoiset2018-01-081-1/+2
* radv/winsys: make IBs read-only for the GPUSamuel Pitoiset2018-01-081-6/+11
* radv/winsys: add RADEON_FLAG_READ_ONLYSamuel Pitoiset2018-01-082-1/+4
* radv/winsys: rework radv_amdgpu_bo_va_op()Samuel Pitoiset2018-01-081-17/+23
* ac: add ac_build_fmin/fmax helpersMarek Olšák2018-01-062-15/+22
* radv: remove unused radv_color_buffer_info::cb_clear_valueXSamuel Pitoiset2018-01-051-2/+0
* radv: enable denorms for 64-bit and 16-bit floatsSamuel Pitoiset2018-01-051-0/+14
* amd/common: correctly detect if we need ring buffersSamuel Pitoiset2018-01-051-7/+9
* amd/common: use ac_image_load when lod is zeroSamuel Pitoiset2018-01-051-1/+3
* radv: limit the scissor bug workaround to Vega 10 and RavenSamuel Pitoiset2018-01-051-1/+6
* ac: rework ac_llvm_extract_elem()Timothy Arceri2018-01-051-3/+3
* ac/radeonsi: add load_tess_coord() to the abiTimothy Arceri2018-01-052-7/+17
* ac/radeonsi: add tcs_rel_ids to the abiTimothy Arceri2018-01-052-8/+8
* ac: add {tcs,tes}_patch_id to the abiTimothy Arceri2018-01-052-8/+8
* ac: move some helpers to ac_llvm_build.cTimothy Arceri2018-01-053-40/+50
* ac: add store_tcs_outputs() to the abiTimothy Arceri2018-01-052-24/+51
* ac: call load_tcs_input() via the abiTimothy Arceri2018-01-051-19/+17
* ac: add load_tes_inputs() to the abiTimothy Arceri2018-01-052-22/+51
* radv: Use correct flush bits for flushing L2 during CB/DB flushes.Bas Nieuwenhuizen2018-01-041-13/+16
* radv: Invalidate L1 for VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT.Bas Nieuwenhuizen2018-01-041-1/+1
* radv/gfx9: reduce the number of input VGPRs for the GS stageSamuel Pitoiset2018-01-041-1/+14
* amd/common: scan if gl_PrimitiveID is used before translating to LLVMSamuel Pitoiset2018-01-045-10/+7
* amd/common: scan if gl_InvocationID is usedSamuel Pitoiset2018-01-042-0/+4
* ac: rename has_sync_file to has_fence_to_handle.Bas Nieuwenhuizen2018-01-042-3/+3
* ac/nir: Handle loading data from compact arrays.Bas Nieuwenhuizen2018-01-041-6/+7
* radv: Allow writing 0 scissors.Bas Nieuwenhuizen2018-01-041-1/+2
* radv: Use correct HTILE expanded words.Bas Nieuwenhuizen2018-01-041-2/+4
* ac: rename has_syncobj_wait -> has_syncobj_wait_for_submitMarek Olšák2018-01-044-7/+7
* radv: Implement binning on GFX9.Bas Nieuwenhuizen2017-12-314-6/+348
* radv: Add flag for enabling binning.Bas Nieuwenhuizen2017-12-312-0/+9
* radv: Also set DCC params for sampling for input attachment usage.Bas Nieuwenhuizen2017-12-291-1/+2
* radv: Enable DCC with transfers.Bas Nieuwenhuizen2017-12-291-2/+1
* radv: Decompress copy destination if formats are incompatible.Bas Nieuwenhuizen2017-12-291-2/+25
* radv: Disable DCC for GENERAL layout and compute transfer dest.Bas Nieuwenhuizen2017-12-294-8/+47
* radv: Don't init DCC metadata during FS resolve.Bas Nieuwenhuizen2017-12-291-5/+0
* radv: Make color meta operations layout aware.Bas Nieuwenhuizen2017-12-295-110/+145
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-25 14:20:51 +0000