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* amd/addrlib: second update for Vega10 + bug fixesMarek Olšák2017-04-0417-2132/+3298
| | | | | | | | | | | | | | | | | | | | | | | Highlights: - Display needs tiled pitch alignment to be at least 32 pixels - Implement Addr2ComputeDccAddrFromCoord(). - Macro-pixel packed formats don't support Z swizzle modes - Pad pitch and base alignment of PRT + TEX1D to 64KB. - Fix support for multimedia formats - Fix a case "PRT" entries are not selected on SI. - Fix wrong upper bits in equations for 3D resource. - We can't support 2d array slice rotation in gfx8 swizzle pattern - Set base alignment for PRT + non-xor swizzle mode resource to 64KB. - Bug workaround for Z16 4x/8x and Z32 2x/4x/8x MSAA depth texture - Add stereo support - Optimize swizzle mode selection - Report pitch and height in pixels for each mip - Adjust bpp/expandX for format ADDR_FMT_GB_GR/ADDR_FMT_BG_RG - Correct tcCompatible flag output for mipmap surface - Other fixes and cleanups Acked-by: Alex Deucher <[email protected]> Acked-by: Nicolai Hähnle <[email protected]>
* radv: Increase descriptor limits.Bas Nieuwenhuizen2017-04-041-14/+14
| | | | | | | | We supported more generally. Decreased the dynamic buffers though, as we only support 16 for uniform+storage. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Acked-by: Dave Airlie <[email protected]>
* radv: Rework guard band calculation.Bas Nieuwenhuizen2017-04-031-40/+15
| | | | | | | | | | | | | | | | | | We want the guardband_x/y to be the largerst scalars such that each viewport scaled by that amount is still a subrange of [-32767, 32767]. The old code has a couple of issues: 1) It used scissor instead of viewport_scissor, potentially taking into account a viewport that is too small and therefore selecting a scale that is too large. 2) Merging the viewports isn't ideal, as for example viewports with boundaries [0,1] and [1000, 1001] would allow a guardband scale of ~30k, while their union [0, 1001] only allows a scale of ~32. The new code just determines the guardband per viewport and takes the minimum. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Acked-by: Dave Airlie <[email protected]>
* radv: Enable VK_KHR_incremental_present.Bas Nieuwenhuizen2017-04-033-1/+15
| | | | | | | Just enabling the driver-independent implementation that Jason did. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* vulkan/wsi: Plumb present regions through the common codeJason Ekstrand2017-04-031-1/+2
| | | | | | Reviewed-by: Lionel Landwerlin <[email protected]> Reviewed-by: Daniel Stone <[email protected]> Acked-by: Dave Airlie <[email protected]>
* radv: fix interp at sample code.Dave Airlie2017-04-041-3/+1
| | | | | | | | | | Interp at sample needs to use the center, since the sample positions it retrieves are relative to the center. This fixes a bunch of CTS tests with multisample_interpolation. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: overhaul fragment shader sample positions.Dave Airlie2017-04-045-51/+87
| | | | | | | | | | | | | | | | | | The current code was broken, and I decided to redesign it instead. This puts the sample positions for all samples into the queue constant descriptor buffer after all the spill/ring descriptors. It then uses a single offset register to point how far into the samples the samples for num_samples are. This saves one user sgpr and means we only generate the sample position data in the rare single case where we need it currently. This doesn't fix the failing CTS tests without the followup fix. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv/ac: fix texture derivative orderingDave Airlie2017-04-041-2/+2
| | | | | | | | | The ordering NIR gives us is correct for the hw, this fixes: dEQP-VK.glsl.texture_functions.texturegrad.* (mainly trigged on isampler/usampler 3d textures.). Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv/ac: round cube array coordinate before fixup.Dave Airlie2017-04-041-1/+5
| | | | | | | | This fixes: dEQP-VK.glsl.texture_functions.texture.samplercubearray* Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: move to using common buffer load format.Dave Airlie2017-04-041-8/+5
| | | | | | | Get rid of usage of SI.vs.load.input. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* amd/addrlib: fix optimized build warningsGrazvydas Ignotas2017-04-031-1/+1
| | | | | | | | All the -Wunused-but-set-variable ones. Found a way to do it with a oneliner. Signed-off-by: Grazvydas Ignotas <[email protected]> Signed-off-by: Marek Olšák <[email protected]>
* radv: fix order of the guardband register emission.Dave Airlie2017-04-021-2/+2
| | | | | | | | | y is vert, x is horiz. Noticed in visual inspection compared to radeonsi. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: enable tessellation shaders.Dave Airlie2017-04-012-9/+10
| | | | | | | | This enables tessellation shaders and sets some values for the maximums. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv/ac: setup lds for tessellationDave Airlie2017-04-011-0/+12
| | | | | | | | This seems to get lost in the rebases, should fix the tessellation demos, crash in llvm. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: add ia_multi_vgt_param tessellation support.Dave Airlie2017-04-011-2/+30
| | | | | | | This just ports the relevant radeonsi pieces. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv/cmd: emit tessellation state.Dave Airlie2017-04-011-4/+109
| | | | | | | | | This emits the tessellation shaders and state to the command stream. It contains the logic to emit the LS/HS shaders. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv/pipeline: handle tessellation shader compilationDave Airlie2017-04-011-0/+142
| | | | | | | | | | | | | | So tess shaders have some circular dependencies, TCS needs the TES primitive mode TES needs the TCS vertices out This builds the nir for each shader first to get the info, executes a tes specific nir pass, then builds the LLVM shaders. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv/ac: handle writing out tess factors.Dave Airlie2017-04-011-0/+238
| | | | | | | | | This ports the code from radeonsi to build the if/endif, and ports the tess factor emission code. This code has an optimisation TODO that we can deal with later. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv/ac: add support for TCS/TES inputs/outputs.Dave Airlie2017-04-011-10/+508
| | | | | | | | | | | | | | | | | This adds support for the tessellation inputs/outputs to the shader compiler, this is one of the main pieces of the patch. It is very similiar to the radeonsi code (post merge we should consider if there are better sharing opportunities). The main differences from radeonsi, is that we can have "compact" varyings for clip/cull/tess factors, and we have to add special handling for these. This consists of treating the const index from the deref different depending on the compactness. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv/ac: add clip support for tess eval shader.Dave Airlie2017-04-011-0/+5
| | | | | | | As this may be the last shader to emit clip distances. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv/ac: hook up tessellation intrinsics.Dave Airlie2017-04-011-1/+34
| | | | | | | This just adds support for the nir intrinsics that tessellation uses. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv/ac: hook up shader information handling for tessellationDave Airlie2017-04-011-0/+26
| | | | | | | | This hooks up the tessellation shader info to the nir values and ctx generated ones. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv/pipeline: start calculating tess stage.Dave Airlie2017-04-012-9/+208
| | | | | | | | | | | This calculates the pipeline state for tessellation. It moves the gs ring calculation down to below where the tessellation shaders will be compiled, as it needs the info from those shaders. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: add tessellation support to variant code.Dave Airlie2017-04-011-6/+9
| | | | | | | This just fills out the rsrc registers for tess shaders. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: add tessellation support to shader namingDave Airlie2017-04-011-1/+3
| | | | | Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: add tess ctrl stage barrier workaround for SI.Dave Airlie2017-04-011-2/+10
| | | | | | | This just ports the workaround from radeonsi. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv/ac: add support for patch inputs to unique index code.Dave Airlie2017-04-011-0/+8
| | | | | | | | This add support for tessellation patch inputs to the code that finds the unique parameter index. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: port polaris vgt vertex reuse workaround.Dave Airlie2017-04-012-1/+18
| | | | | | | | This ports the VGT_VERTEX_REUSE register settings for Polaris GPUs from radeonsi. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: configure tessellation distribution register.Dave Airlie2017-04-011-4/+12
| | | | | | | This just takes the radeonsi values. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv/ac: setup tessellation shader inputs.Dave Airlie2017-04-011-1/+81
| | | | | | | | This just configures all the register inputs for the tessellation related stages. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv/ac: setup tess rings on compiler side.Dave Airlie2017-04-012-1/+14
| | | | | | | | This just sets up the necessary pointers on the compiler side for the rings needed for tessellation. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: add tessellation ring allocation support. (v2)Dave Airlie2017-04-013-13/+203
| | | | | | | | | | | | This patch adds support for the offchip rings for storing tessellation factors and attribute data. It includes the register setup for the TF ring v2: always do tess ring size calcs (Bas) Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: add support for some device specific tess information.Dave Airlie2017-04-012-0/+8
| | | | | Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv/ac: add tess changes to shader keys/infoDave Airlie2017-04-011-0/+40
| | | | | | | | This adds the tess pieces for shader keys and shader info, it adds the necessary bits to the vertex key/info as well. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: add tess shader stage user data support.Dave Airlie2017-04-011-7/+38
| | | | | | | | This just adds support for tess to the shader stage conversion and emits the per-stage descriptors/constants for tess stages. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: use defines for ring descriptor offsets.Dave Airlie2017-04-012-4/+11
| | | | | Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: add helper function to denote if tess is enabled on a pipeline.Dave Airlie2017-04-011-0/+5
| | | | | Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: handle clip dist in es outputs.Dave Airlie2017-04-011-2/+1
| | | | | Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: drop unneeded startDave Airlie2017-04-011-2/+2
| | | | | Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: fixup geometry clip emission since using the geom passDave Airlie2017-04-011-1/+2
| | | | | | Fixes: 2b35b60d: radv: move to using nir clip/cull merge pass. Signed-off-by: Dave Airlie <[email protected]>
* radv: Use the guard band.Bas Nieuwenhuizen2017-03-303-13/+90
| | | | | Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: Prepare for not using the guard band for lines & points.Bas Nieuwenhuizen2017-03-303-0/+32
| | | | | | | | | | | Vulkan Clipping is defined in terms of vertices, the scissor based clipping happens on pixels. There is a difference with points and lines, as a vertex can be outside the viewport while some pixels are in. On Vulkan thoise pixels shouldn't be drawn, while they would be with the guardband. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: Drop the default viewport when 0 viewports are given.Bas Nieuwenhuizen2017-03-301-17/+2
| | | | | Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: Set proper viewport & scissor for meta draws.Bas Nieuwenhuizen2017-03-306-75/+214
| | | | | Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* Partially revert "amd/addrlib: silence warnings" to fix builds with DEBUGMarek Olšák2017-03-303-6/+6
| | | | This partially reverts commit 8a74140a21fe6b0d2e8a60b065b890f797f2db51.
* radeonsi/gfx9: image descriptor changes in immutable fieldsMarek Olšák2017-03-301-0/+6
| | | | | | | The border color swizzle logic was copied from Vulkan. It doesn't make any sense to me, but it passes all piglits except the stencil ones. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: init_config changesMarek Olšák2017-03-301-0/+4
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: CP DMA changesMarek Olšák2017-03-301-0/+1
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: add IB parser supportMarek Olšák2017-03-303-19/+36
| | | | | | | | | Both GFX6 and GFX9 fields are printed next to each other in parsed IBs. The Python script parses both headers like one stream and tries to merge all definitions. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: add GFX9 and VEGA10 enumsMarek Olšák2017-03-301-3/+5
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
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