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* radv: Invert condition for all samples identical during resolve.Bas Nieuwenhuizen2017-12-281-1/+1
| | | | | | | | the samples_identical instruction returns 0 if they are differet, so we have to do the extra work if the result is 0, not if it is != 0. Fixes: f4e499ec791 "radv: add initial non-conformant radv vulkan driver" Reviewed-by: Dave Airlie <[email protected]>
* radv: don't do format replacement on tc compat htile surfaces.Dave Airlie2017-12-281-1/+2
| | | | | | | | | | | | For copies the texture unit needs to know the depth format so it can read the htile data properly. This fixes: dEQP-VK.renderpass.suballocation.formats.d32_sfloat_s8_uint.load.clear Fixes: ad3d98da9f (radv: enable tc compatible htile for d32s8 also.) Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv/gfx9: use correct stencil format for tc compat htile.Dave Airlie2017-12-281-4/+7
| | | | | | | | | | | This needs to correspond to the bit depth of the Z plane. noticed in passing reading amdvlk. Fixes: fc6c77e162df3 (radv: fix TC-compat HTILE with VK_FORMAT_D32_SFLOAT_S8_UINT on Vega) Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: set some dcc parameters depending on if texture will be sampledDave Airlie2017-12-271-1/+10
| | | | | | | | | | This is ported from amdvlk which sets the independent 64b blocks only for image which will sample dcc. I'm not sure how to port this to radeonsi. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv/radeonsi: set dcc min uncompressed properly for APUs.Dave Airlie2017-12-271-0/+10
| | | | | | | This is ported from amdvlk. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* amd/common/radv/radeonsi: use register defines for dcc block sizes.Dave Airlie2017-12-271-3/+3
| | | | | | | | These are just taken from amdvlk, we probably knew these already, but may as well port them now. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: Fix DCC compatible formats.Bas Nieuwenhuizen2017-12-231-1/+1
| | | | | | | | | DCC was disabled when the image format is !!supported, which is one ! too many. Ironically the commit that introduced it was supposed to lead to more DCC use ... Fixes: 969537d9358 "radv: Add support for more DCC compression with VK_KHR_image_format_list." Reviewed-by: Dave Airlie <[email protected]>
* radv: reduce the number of small surfaces that need CMASK or DCCSamuel Pitoiset2017-12-221-1/+1
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv/meta: fix blit paths for depth/stencil (v2.1)Dave Airlie2017-12-222-64/+80
| | | | | | | | | | | | | | This fixes the layout issue for the blit path as well. This fixes: dEQP-VK.api.copy_and_blit.core.blit_image.all_formats.depth_stencil.d32_sfloat_s8_uint_d32_sfloat_s8_uint* v2: use compatible render passes. v2.1: use enum Reviewed-by: Bas Nieuwenhuizen <[email protected]> Cc: "17.2 17.3" <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: handle depth/stencil image copy with layouts better. (v3.1)Dave Airlie2017-12-224-65/+106
| | | | | | | | | | | | | | | | | | | If we are doing a general->general transfer with HIZ enabled, we want to hit the tile surface disable bits in radv_emit_fb_ds_state, however we never get the current layout to know we are in general and meta hardcoded the transfer layout which is always tile enabled. This fixes: dEQP-VK.api.copy_and_blit.core.image_to_image.all_formats.depth_stencil.d32_sfloat_s8_uint_d32_sfloat_s8_uint.optimal_general dEQP-VK.api.copy_and_blit.core.image_to_image.all_formats.depth_stencil.d32_sfloat_s8_uint_d32_sfloat_s8_uint.general_general v2: refactor some shared helpers for blit patches v3: we only need multiple render passes as they should be compatible. v3.1: use enum (Bas) Reviewed-by: Bas Nieuwenhuizen <[email protected]> Cc: "17.2 17.3" <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: refactor blit2d pipeline creationDave Airlie2017-12-221-78/+33
| | | | | | | | This just refactors the gfx9 blit2d pipeline creation to be less lines of code. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv/gfx9: add support for 3d images to blit 2d pathsDave Airlie2017-12-222-23/+97
| | | | | | | | | | This add support for a 3D image reading path to the blit 2d paths, like I did for the clear paths. Fixes: e38685cc62e 'Revert "radv: disable support for VEGA for now."' Reviewed-by: Bas Nieuwenhuizen <[email protected]> Tested-by: Alex Smith <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv/gfx9: add 3d sampler image->buffer copy shader. (v3)Dave Airlie2017-12-222-18/+59
| | | | | | | | | | | | | | | | | | On GFX9 we must access 3D textures with 3D samplers AFAICS. This fixes: dEQP-VK.api.image_clearing.core.clear_color_image.3d.single_layer on GFX9 for me. v1.1: fix tex->sampler_dim to dim v2: send layer in from outside v3: don't regress on pre-gfx9 Fixes: e38685cc62e 'Revert "radv: disable support for VEGA for now."' Reviewed-by: Bas Nieuwenhuizen <[email protected]> Tested-by: Alex Smith <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: fix surface max layer count (v2)Dave Airlie2017-12-221-7/+7
| | | | | | | | | | | looking at traces I noticed we'd set slice_max too large sometimes. This should fix it. v2: fix missing - 1 Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: fix issue with multisample positions and interp_var_at_sample.Dave Airlie2017-12-221-1/+2
| | | | | | | | | | | | | | | | This fixes vmfaults seen on vega with: dEQP-VK.pipeline.multisample_interpolation.sample_interpolate_at_single_sample_.128_128_1.samples_1 These were caused by the don't allocate cmask but it was just accidental. The actual problem was the shader was trying to get the sample positions from a buffer, but the buffer was never getting configured to contain them, as the previous shader never needed them. Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Fixes: 1171b304f3 (radv: overhaul fragment shader sample positions.) Signed-off-by: Dave Airlie <[email protected]>
* radv/gfx9: fix primitive topology when adjacency is usedSamuel Pitoiset2017-12-211-1/+1
| | | | | | | | Found by inspection. Cc: 17.3 <[email protected]> Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: properly load unused gl_LocalInvocationID/gl_WorkGroupID componentsSamuel Pitoiset2017-12-191-2/+5
| | | | | | | F1 2017 looks good now. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: store pipeline stages that need push constantsSamuel Pitoiset2017-12-192-0/+4
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: remove one useless check in radv_flush_constants()Samuel Pitoiset2017-12-191-1/+2
| | | | | | | pipeline->layout can't be NULL now. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: add assertions to make sure pipeline layout objects are validSamuel Pitoiset2017-12-191-0/+2
| | | | | | | The spec requires it. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: create pipeline layout objects for all meta operationsSamuel Pitoiset2017-12-194-2/+80
| | | | | | | | | They are dummy objects but the spec requires layout to not be NULL, this just makes sure we are creating valid pipeline layout objects. This will allow us to remove some useless checks. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: Use a sort for rebuilding the sparse buffer bo list.Bas Nieuwenhuizen2017-12-191-21/+24
| | | | | | | | | It uses slightly more memory (though still bounded by the number of mapped ranges), but gives less quadratic behavior. Cuts 4 minutes from the runtime of the CTS *.sparse.* tests. Reviewed-by: Eric Engestrom <[email protected]>
* radv: Advertise sync fd import and export.Bas Nieuwenhuizen2017-12-181-4/+15
| | | | | | Passes dEQP-VK.*.sync_fd.* Reviewed-by: Dave Airlie <[email protected]>
* radv: Implement sync file import/export for fences & semaphores.Bas Nieuwenhuizen2017-12-181-28/+87
| | | | Reviewed-by: Dave Airlie <[email protected]>
* radv/amdgpu: wrap sync fd import/export.Bas Nieuwenhuizen2017-12-182-0/+26
| | | | Reviewed-by: Dave Airlie <[email protected]>
* radv: remove useless radv_cmask_info::base_address_regSamuel Pitoiset2017-12-181-1/+0
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* amd/common: add ac_vgt_gs_mode() helperSamuel Pitoiset2017-12-181-26/+6
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* amd/common: add ac_get_cb_shader_mask() helperSamuel Pitoiset2017-12-181-33/+1
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* Revert "radv: do not load unused gl_LocalInvocationID/gl_WorkGroupID components"Samuel Pitoiset2017-12-181-5/+2
| | | | | | | | | | | | | This reverts commit 2294d35b243dee15af15895e876a63b7d22e48cc. We can't do this without adjusting the input SGPRs/VGPRs logic. For now, just revert it. I will send a proper solution later. It fixes a rendering issue in F1 2017 that CTS didn't catch up. Signed-off-by: Samuel Pitoiset <[email protected]> Tested-by: Alex Smith <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: port merge tess info from anvDave Airlie2017-12-181-0/+40
| | | | | | | | | | | anv merges the tess info correctly, but radv wasn't doing this. This fixes hangs in dEQP-VK.tessellation.winding.default_domain.hlsl_triangles_ccw Fixes: 60fc0544e0 (radv/pipeline: handle tessellation shader compilation) Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: Add external fence support.Bas Nieuwenhuizen2017-12-182-0/+22
| | | | Reviewed-by: Dave Airlie <[email protected]>
* radv: Implement VK_KHR_external_fence_fd.Bas Nieuwenhuizen2017-12-182-0/+48
| | | | Reviewed-by: Dave Airlie <[email protected]>
* radv: Implement fences based on syncobjs.Bas Nieuwenhuizen2017-12-183-15/+109
| | | | Reviewed-by: Dave Airlie <[email protected]>
* radv: Add syncobj signal/reset/wait to winsys.Bas Nieuwenhuizen2017-12-182-0/+44
| | | | Reviewed-by: Dave Airlie <[email protected]>
* radv: Fix multi-layer blits.Bas Nieuwenhuizen2017-12-181-25/+24
| | | | | | | | | We did not set the layer correctly for the dst, as we would keep using the base layer. Same for the source image. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102710 CC: <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: export SampleMask from pixel shaders at full rateSamuel Pitoiset2017-12-141-5/+6
| | | | | | | | | | | Use 16_ABGR instead of 32_ABGR if Z isn't written. Ported from RadeonSI. No CTS regressions on Polaris. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: do not load the local invocation index when it's unusedSamuel Pitoiset2017-12-141-1/+1
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: do not load unused gl_LocalInvocationID/gl_WorkGroupID componentsSamuel Pitoiset2017-12-141-3/+8
| | | | | | | | We should also not load the input SGPRs and VGPRS, but let's start with this for now. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: set FORCE_SIMD_DIST(1) for compute when profitableSamuel Pitoiset2017-12-141-0/+14
| | | | | | | Ported from RadeonSI. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: calculate best compute resource limitsSamuel Pitoiset2017-12-141-1/+14
| | | | | | | Ported from RadeonSI. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: store the dispatch initiator into the deviceSamuel Pitoiset2017-12-143-11/+12
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: always emit all compute block componentsSamuel Pitoiset2017-12-141-10/+5
| | | | | | | | | The number of grid components is always 3 when gl_NumWorkGroups is declared, because it relies on the number of components of nir_instrinsic_load_num_work_groups. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: Don't advertise VK_EXT_debug_report.Bas Nieuwenhuizen2017-12-141-1/+0
| | | | | | | We never supported it. Missed during copy and pasting. Fixes: 17201a2eb0b "radv: port to using updated anv entrypoint/extension generator." Reviewed-by: Samuel Pitoiset <[email protected]>
* radv: Don't use local BOs when allocating with export options.Bas Nieuwenhuizen2017-12-101-1/+3
| | | | | | | | | If the app does not plan to put a buffer or image in it (why? But it is allowed and CTS does it), they do not need to allocate it with the deciate allocation struct. Fixes: a639d40f133 "radv: add support for local bos. (v3)" Reviewed-by: Dave Airlie <[email protected]>
* radv: do not print ASM to stderr when dumping shadersSamuel Pitoiset2017-12-081-1/+1
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv/winsys: implement query_value()Samuel Pitoiset2017-12-082-0/+72
| | | | | | | | | Might be useful to know the VRAM/GTT usage, the number of VRAM CPU page faults, etc. Nothing is currently using that new interface, but it's a first step. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: remove useless check radv_set_dcc_need_cmask_elim_pred()Samuel Pitoiset2017-12-081-2/+1
| | | | | | | emit_fast_color_clear() already checks that. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: remove useless checks in radv_set_{color,depth}_clear_regs()Samuel Pitoiset2017-12-081-4/+2
| | | | | | | Already checked by the respective callers. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: only re-mit the index type when it changesSamuel Pitoiset2017-12-082-10/+24
| | | | | | | | | dota2 binds a ton of index buffers but the type is always 16-bit. Note that we have to invalidate the type when switching from indexed draws to normal draws. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: only reset command buffers that are not in the initial stateSamuel Pitoiset2017-12-081-4/+9
| | | | | | | | dota2 always calls vkResetCommandBuffer() before vkBeginCommandBuffer() which is quite useless. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
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