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* mesa: include mtypes.h lessMarek Olšák2018-04-125-0/+7
| | | | | | | | | | - remove mtypes.h from most header files - add main/menums.h for often used definitions - remove main/core.h v2: fix radv build Reviewed-by: Brian Paul <[email protected]>
* radv: Implement VK_EXT_vertex_attribute_divisor.Bas Nieuwenhuizen2018-04-126-11/+50
| | | | | | | Pretty straight forward, just pass the divisors through the shader key and then do a LLVM divide. Reviewed-by: Samuel Pitoiset <[email protected]>
* radv: fix radv_layout_dcc_compressed() when image doesn't have DCCSamuel Pitoiset2018-04-121-1/+1
| | | | | | | | | | | | | | | | num_dcc_levels means that DCC is supported, but this doesn't mean that it's enabled by the driver. Instead, we should rely on radv_image_has_dcc(). This fixes some multisample regressions since 0babc8e5d66 ("radv: fix picking the method for resolve subpass") on Vega. This is because the resolve method changed from HW to FS, but those fails are totally unexpected, so there might some differences between Polaris and Vega here. Fixes: 44fcf587445 ("radv: Disable DCC for GENERAL layout and compute transfer dest.") Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: add radv_decompress_resolve_{subpass}_src() helpersSamuel Pitoiset2018-04-124-54/+73
| | | | | | | | This helper shares common code before resolving using either a fragment or a compute shader. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: add radv_init_dcc_control_reg() helperSamuel Pitoiset2018-04-121-32/+52
| | | | | | | And add some comments. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: Enable RB+ on Raven.Bas Nieuwenhuizen2018-04-111-1/+2
| | | | Reviewed-by: Samuel Pitoiset <[email protected]>
* vulkan: fix build issue on android (both anv/radv)Tapani Pälli2018-04-111-3/+3
| | | | | | | | | | Fixes linking errors against: anv_GetPhysicalDeviceImageFormatProperties2KHR radv_GetPhysicalDeviceImageFormatProperties2KHR Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* vulkan: Drop vk_android_native_buffer.xmlJason Ekstrand2018-04-103-16/+8
| | | | | | | | All the information in vk_android_native_buffer.xml is now in vk.xml. The only exception is the extension type attribute which we can work around in the generators while we wait for the XML to be fixed. Reviewed-by: Dylan Baker <[email protected]>
* radv: Enable RB+ where possible.Bas Nieuwenhuizen2018-04-113-6/+151
| | | | | | | | | | | | | | | According to Marek, not enabling it on Stoney has a significant negative performance impact. (And I guess this might impact performance on Raven as well) The register settings are pretty much copied from radeonsi. I did not put this in the pipeline as that would make the pipeline more dependent on the format which mean we would have to have more pipelines for the meta shaders. v2: Don't clear RB+ regs if not enabled as the CLEAR_STATE packet does already. Reviewed-by: Samuel Pitoiset <[email protected]>
* radv: fix picking the method for resolve subpassSamuel Pitoiset2018-04-101-1/+1
| | | | | | | | | | | The source and destination image parameters were swapped. No CTS changes on Polaris10, but I suspect this might fix something. Fixes: 2a04f5481df ("radv/meta: select resolve paths") Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: add shader BOs to the list at pipeline bind timeSamuel Pitoiset2018-04-101-3/+15
| | | | | | | | | | | | Otherwise, the shader BOs are not added to the list on SI because prefetching isn't supported. Calling radv_cs_add_buffer() in the prefetch codepath was a bad idea. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105952 Fixes: 4ad7595f35 ("radv: rename radv_emit_prefetch() to radv_emit_prefetch_L2") Signed-off-by: Samuel Pitoiset <[email protected]> Tested-by: Turo Lamminen <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* ac/surface: don't set the display flag for obviously unsupported cases (v2)Marek Olšák2018-04-101-0/+1
| | | | | | | This enables the tile swizzle for some cases of the displayable micro mode, and it also fixes an addrlib assertion failure on Vega. Reviewed-by: Michel Dänzer <[email protected]>
* radv: Always reset draw user SGPRs after secondary command buffer.Bas Nieuwenhuizen2018-04-091-14/+3
| | | | | | | | As we sometimes reset them to -1, -1 does not mean that they are not written by the secondary command buffer. Fixes: ad11fc3571 "radv: don't emit unneeded vertex state." Reviewed-by: Samuel Pitoiset <[email protected]>
* radv: Don't set instance count using predication.Bas Nieuwenhuizen2018-04-091-1/+1
| | | | | | | | | | The packet can sometimes be skipped, but we still think the change takes effect. This just makes the packet always take effect. Fixes: ad11fc3571 "radv: don't emit unneeded vertex state." Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105942 Reviewed-by: Samuel Pitoiset <[email protected]>
* radv: fix prefetching of vertex shader and VBOs on SISamuel Pitoiset2018-04-091-1/+1
| | | | | | | | Forgot one check... Too many mistakes for a simple change. Fixes: f1d7c16e85 ("radv: fix prefetching compute shaders on CIK and older chips") Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: implement VK_AMD_shader_core_propertiesSamuel Pitoiset2018-04-092-0/+41
| | | | | | | Simple extension that only returns information for AMD hw. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: add RADV_NUM_PHYSICAL_VGPRS constantSamuel Pitoiset2018-04-092-2/+6
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: add radv_get_num_physical_sgprs() helperSamuel Pitoiset2018-04-092-11/+10
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: add radv_image_is_tc_compat_htile() helperSamuel Pitoiset2018-04-095-12/+21
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: add radv_use_dcc_for_image() helperSamuel Pitoiset2018-04-091-30/+68
| | | | | | | And add some TODOs. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: rename radv_image_is_tc_compat_htile()Samuel Pitoiset2018-04-091-3/+3
| | | | | | | | | ... to radv_use_tc_compat_htile_for_image(). This function name makes more sense to me because we want to know if and only if TC-compat HTILE should be used. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: simplify a check in radv_initialise_color_surface()Samuel Pitoiset2018-04-091-1/+1
| | | | | | | | If the image has FMASK metadata, the number of samples is > 1 because radv_image_can_enable_fmask() handles that already. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: clean up radv_vi_dcc_enabled()Samuel Pitoiset2018-04-093-8/+12
| | | | | | | And rename to radv_dcc_enabled() to be consistent. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: clean up radv_htile_enabled()Samuel Pitoiset2018-04-091-6/+9
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: add radv_image_has_{cmask,fmask,dcc,htile}() helpersSamuel Pitoiset2018-04-099-36/+72
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: add radv_get_cmask_fast_clear_value() helperSamuel Pitoiset2018-04-091-1/+22
| | | | | | | | DCC for MSAA textures are currently unsupported but that will be used later on. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: add radv_clear_{cmask,dcc} helpersSamuel Pitoiset2018-04-094-15/+29
| | | | | | | | They will help for DCC MSAA textures and if we support mipmaps in the future. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: don't pass the pipeline to radv_flush_constants()Samuel Pitoiset2018-04-061-5/+5
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: rename radv_cmd_buffer_update_vertex_descriptors()Samuel Pitoiset2018-04-061-2/+3
| | | | | | ... to radv_flush_vertex_descriptors(). Signed-off-by: Samuel Pitoiset <[email protected]>
* radv: do not try to skip draw calls when VBOs upload failedSamuel Pitoiset2018-04-061-14/+6
| | | | | | | | | This is unnecessary because we record an error which should be returned by vkEndCommandBuffer(), and the app shouldn't submit a command buffer when this happens. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: fix prefetching compute shaders on CIK and older chipsSamuel Pitoiset2018-04-061-7/+8
| | | | | | | | Because the check was moved to radv_emit_prefetch_L2(). Fixes: 4ad7595f35 ("radv: rename radv_emit_prefetch() to radv_emit_prefetch_L2()") Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: only enable PERFECT_ZPASS_COUNTS for precision occlusion queriesSamuel Pitoiset2018-04-063-6/+35
| | | | | | | | | | This unnecessary when the precision bit flag is not set, and this might hurt performance. The Vulkan explains that not setting VK_QUERY_CONTROL_PRECISE_BIT might be more efficient on some implementations. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: enable the Polaris small primitive filter controlSamuel Pitoiset2018-04-061-0/+15
| | | | | | | | | | | Enable it directly in the preamble, but do not enable line on Polaris10/11/12 because there is a hw bug. There is possibly an issue when MSAA is off, but this doesn't regress any CTS and AMDVLK doesn't have a workaround as well. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: implement a fast prefetch path for the vertex stageSamuel Pitoiset2018-04-051-10/+30
| | | | | | | | This allows to start draws as soon as possible. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Tested-by: Dieter Nützel <[email protected]>
* radv: rename radv_emit_prefetch() to radv_emit_prefetch_L2()Samuel Pitoiset2018-04-051-19/+11
| | | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Tested-by: Dieter Nützel <[email protected]>
* radv: use a mask for VBOs and shaders prefetchingSamuel Pitoiset2018-04-052-27/+51
| | | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Tested-by: Dieter Nützel <[email protected]>
* radv: implement out-of-order rasterization when it's safe on VI+Samuel Pitoiset2018-04-046-3/+279
| | | | | | | | | | | | | | | | Disabled by default for now, it can be enabled with RADV_PERFTEST=outoforder. No CTS regressions on Polaris, and all Vulkan games I tested look good as well. Expect small performance improvements for applications where out-of-order rasterization can be enabled by the driver. Loosely based on RadeonSI. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: change blend_enable field to use four bits per CBSamuel Pitoiset2018-04-041-3/+5
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: scan which color blend attachments are enabledSamuel Pitoiset2018-04-041-0/+2
| | | | | | | With cb_target_enabled_4bit in order to have four bits per CB. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: put more fields in radv_blend_stateSamuel Pitoiset2018-04-041-20/+17
| | | | | | | Some will be used for further optimizations (ie. out-of-order rast). Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: do not always disable dual quad mode when chip has RbPlusSamuel Pitoiset2018-04-041-3/+17
| | | | | | | For GFX9+ only, RadeonSI does this too. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: don't use the SPI barrier management bug workaroundSamuel Pitoiset2018-04-041-0/+5
| | | | | | | Ported from RadeonSI. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: mask out high VM address bits in registers where neededSamuel Pitoiset2018-04-043-19/+19
| | | | | | | Ported from RadeonSI. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: enable VK_EXT_shader_viewport_index_layerSamuel Pitoiset2018-04-032-0/+2
| | | | | | | | The driver already supports exporting the Layer and ViewportIndex built-ins from vertex or tessellation shaders. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* ac/nir: Fix include for LLVMAddPromoteMemoryToRegisterPassMike Lothian2018-04-021-0/+3
| | | | | | | | | Include llvm-c/Transforms/Utils.h with the newest LLVM 7 Signed-of-by: Mike Lothian <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]> Tested-by: Dieter Nützel <[email protected]> Signed-off-by: Marek Olšák <[email protected]>
* radv: set SAMPLE_RATE to the number of samples of the current fbSamuel Pitoiset2018-03-303-4/+16
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* util: Move util_is_power_of_two to bitscan.h and rename to ↵Ian Romanick2018-03-291-2/+2
| | | | | | | | | | | util_is_power_of_two_or_zero The new name make the zero-input behavior more obvious. The next patch adds a new function with different zero-input behavior. Signed-off-by: Ian Romanick <[email protected]> Suggested-by: Matt Turner <[email protected]> Reviewed-by: Alejandro Piñeiro <[email protected]>
* radv: fix scanning output_usage_mask with structsSamuel Pitoiset2018-03-291-4/+52
| | | | | | | | | | | | To fix a regression in: dEQP-VK.spirv_assembly.instruction.graphics.variable_init.output.struct And the following regressions (Polaris only): dEQP-VK.glsl.indexing.varying_array.* Fixes: f3275ca01c ("ac/nir: only enable used channels when exporting parameters") Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: enable VK_AMD_shader_trinary_minmax extensionDaniel Schürmann2018-03-292-0/+2
| | | | | Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* ac/nir: Add workaround for GFX9 buffer views.Bas Nieuwenhuizen2018-03-291-0/+1
| | | | | | | | | | | | | | | | | | | | | On GFX9 whether the buffer size is interpreted as elements or bytes depends on whether IDXEN is enabled in the instruction. If the index is a constant zero, LLVM optimizes IDXEN to 0. Now the size in elements is interpreted in bytes which of course results in out of bounds accesses. The correct fix is most likely to disable the LLVM optimization, but we need something to work with LLVM <= 6.0. radeonsi does the max between stride and element count on the CPU but that results in the size intrinsics returning the wrong size for the buffer. This would cause CTS errors for radv. v2: Also include the store changes. Fixes: e38685cc62e 'Revert "radv: disable support for VEGA for now."' Reviewed-by: Samuel Pitoiset <[email protected]>
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