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* amdgpu/addrlib: Rewrite tile mode optmization codeXavi Zhang2017-03-301-3/+2
| | | | Note: remove reference to degrade4Space and use opt4Space instead.
* radv: move to using nir clip/cull merge pass.Dave Airlie2017-03-301-0/+1
| | | | | | | | | | Doing this before tessellation makes doing some bits of tessellation a bit cleaner. It also cleans up a bit of the llvm generator code. Reviewed-by: Edward O'Callaghan <[email protected]> Acked-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: Enable sparseBinding feature.Bas Nieuwenhuizen2017-03-291-4/+8
| | | | | Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv/amdgpu: Use reference counting for bos.Bas Nieuwenhuizen2017-03-292-0/+11
| | | | | | | | | | | | | Per the Vulkan spec, memory objects may be deleted before the buffers and images using them are deleted, although those resources then cannot be used except for deletion themselves. For the virtual buffers, we need to access them on resource destruction to unmap the regions, so this results in a use-after-free. Implement reference counting to avoid this. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: Implement sparse memory binding.Bas Nieuwenhuizen2017-03-291-4/+80
| | | | | | | v2: Only submit when semaphores are specified. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: Implement sparse image creation.Bas Nieuwenhuizen2017-03-292-2/+22
| | | | | Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: Implement sparse buffer creation.Bas Nieuwenhuizen2017-03-292-2/+21
| | | | | Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv/amdgpu: Add winsys implementation of virtual buffers.Bas Nieuwenhuizen2017-03-294-26/+349
| | | | | | | | | v2: - Added comments. - Fixed a double unmap bug. - Actually unmap the non-edge old ranges. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: Assert when setting 0 registers in a sequence.Bas Nieuwenhuizen2017-03-291-0/+4
| | | | | | | To catch more of those hangs early. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Acked-by: Dave Airlie <[email protected]>
* radv: only emit ps_input_cntl is we have any to outputDave Airlie2017-03-281-3/+6
| | | | | | | Otherwise we get GPU hangs. Reported-by: Alex Smith <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: move shader stages calculation to pipeline.Dave Airlie2017-03-283-9/+10
| | | | | | | | With tess this becomes a bit more complex. so move to pipeline for now. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: move pa_cl_vs_out_cntl calculation to pipelineDave Airlie2017-03-283-17/+32
| | | | | | | This also takes the side band setting code from radeonsi. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: move calculating fragment shader i/os to pipeline.Dave Airlie2017-03-283-63/+77
| | | | | | | There is no need to calculate this on each command submit. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: move shader_z_format calculation to pipeline.Dave Airlie2017-03-283-4/+8
| | | | | | | No need to recalculate this every time. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: move db_shader_control calculation to pipeline.Dave Airlie2017-03-283-16/+20
| | | | | | | There is no need to recalculate this every time. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: move vgt_gs_mode value to pipeline.Dave Airlie2017-03-283-27/+30
| | | | | | | No need to recalculate this everytime. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: rework vertex/export shader output handlingDave Airlie2017-03-282-33/+39
| | | | | | | | | In order to faciliate adding tess support, split the vs/es output info into a separate block, so we make it easier to have the tess shaders export the same info. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: fix ia_multi_vgt_param for instanced vs indirect draw.Dave Airlie2017-03-283-13/+15
| | | | | | | | The logic was different than radeonsi, fix it up before adding tess support. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: handle NULL multisample state.Dave Airlie2017-03-281-8/+12
| | | | | | | | If rasterization is disabled, we can get a NULL multisample state. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: flush DB cache before and after HTILE decompress.Bas Nieuwenhuizen2017-03-281-0/+6
| | | | | | | | | | | It reads @ writes the DB cache, and we haven't flushed dst caches yet, so DB cache may be stale. Also the user might be shader read (and probably is), so also flush after. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]> CC: <[email protected]> Fixes: f4e499ec791 ("radv: add initial non-conformant radv vulkan driver")
* radv: don't emit no color formats. (v3)Dave Airlie2017-03-281-2/+19
| | | | | | | | | | | | | | | If we had no rasterization, we'd emit SPI color format as all 0's the hw dislikes this, add the workaround from radeonsi. Found while debugging tessellation v2: handle at pipeline stage, we have to handle it after we process the fragment shader. (Bas) v3: simplify even further, remove old fallback. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: Invalidate L2 for TRANSFER_WRITE barriersAlex Smith2017-03-231-1/+1
| | | | | | | | | | | | CP DMA and PKT3_WRITE_DATA (in CmdUpdateBuffer) don't (currently) write through L2. Therefore, to make these writes visible to later accesses we must invalidate L2 rather than just writing it back, to avoid the possibility that stale data is read through L2. Cc: "17.0" <[email protected]> Signed-off-by: Alex Smith <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: consistently use ifndef guards over pragma onceEmil Velikov2017-03-221-1/+4
| | | | | | | | | | Namely: annotate the single file which is not using a ifndef guard - vk_format.h Signed-off-by: Emil Velikov <[email protected]> Acked-by: Vedran Miletić <[email protected]> Acked-by: Juha-Pekka Heikkila <[email protected]> Reviewed-by: Edward O'Callaghan <[email protected]>
* radv: move KHR_get_physical_device_properties2 to instance props.Dave Airlie2017-03-211-4/+4
| | | | | | | | | This is an instance property not a device one. Fixes: dEQP-VK.api.info.device.extensions Signed-off-by: Dave Airlie <[email protected]>
* radv: drop illegal DB format error.Dave Airlie2017-03-211-3/+0
| | | | | | We'll get this if we have a stencil only setup. Signed-off-by: Dave Airlie <[email protected]>
* radv: fix logic for when to flush on multiple CS emissionDave Airlie2017-03-201-8/+8
| | | | | | | | | The current code evaluated to always true, we only want to flush on the first submit. Rename the variable to do_flush, and only emit on the first iteration. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv/meta: fix image clears for r4g4 format.Dave Airlie2017-03-201-0/+8
| | | | | | | This just uses an 8-bit clear and packs the values. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* Revert "radv: fallback to an in-memory cache when no pipline cache is provided"Dave Airlie2017-03-203-13/+6
| | | | | | | | | | | This reverts commit 2845a108a9a8bd4b0e6e9b590c976452fb99eb10. This break VK-GL-CTS randomly. ./deqp-vk --deqp-case=dEQP-VK.texture.filtering.3d.formats.r4g4b4a4* bounces around here from 6/6 to 3/6 or 4/6 to hanging. Signed-off-by: Dave Airlie <[email protected]>
* radv: fix primitive reset index emissionDave Airlie2017-03-201-1/+1
| | | | | | | | | | This was meant to be checking the index type to get the correct index not the last emitted one. This fixes: dEQP-VK.pipeline.input_assembly.primitive_restart.index_type_uint32.triangle_strip_with_adjacency Reviewed-by: Bas Nieuwenhuizen <[email protected]> Cc: "13.0 17.0" <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: make sure gs copy shader is retrieved from the cache with the variantTimothy Arceri2017-03-171-4/+9
| | | | | | | Apps can limit the size of the cache via VkAllocationCallbacks so we can't be sure that both are always in the cache. Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: fallback to an in-memory cache when no pipline cache is providedTimothy Arceri2017-03-173-6/+13
| | | | Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: always create an fallback pipeline cacheTimothy Arceri2017-03-172-0/+20
| | | | | | | This will be used as an in-memory cache when a pipeline cache is not provided by the app. Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: move cache check inside insert and search functionsTimothy Arceri2017-03-172-16/+20
| | | | | | | This will allow us to use fallback in-memory and on-disk caches should the app not provide a pipeline cache. Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* Revert "radv: Emit cache flushes before CP DMA."Bas Nieuwenhuizen2017-03-161-3/+0
| | | | | | | | This reverts commit cce43f6d8c40222099badaf52344d6a0eed993f3. Redundant, as the flush already happens at si_cp_dma_prepare. Acked-by: Dave Airlie <[email protected]>
* radv: do not open random render node(s)Emil Velikov2017-03-151-12/+36
| | | | | | | | | | | | | | | | drmGetDevices2() provides us with enough flexibility to build heuristics upon. Opening a random node on the other hand will wake up the device, regardless if it's the one we're interested or not. v2: Rebase. v3: Return VK_ERROR_INCOMPATIBLE_DRIVER for no devices (Ilia) Cc: Michel Dänzer <[email protected]> Cc: Dave Airlie <[email protected]> Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> (v1) Reviewed-by: Eric Engestrom <[email protected]> (v1) Tested-by: Mike Lothian <[email protected]>
* radv/winsys: use drmGetDevice2 APIEmil Velikov2017-03-151-2/+2
| | | | | | | | | | | | | Analogous to previous commit v2: Add explicit require_libdrm check. Cc: Dave Airlie <[email protected]> Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Michel Dänzer <[email protected]> (v1) Reviewed-by: Bas Nieuwenhuizen <[email protected]> (v1) Reviewed-by: Eric Engestrom <[email protected]> (v1) Tested-by: Mike Lothian <[email protected]>
* util/sha1: rework _mesa_sha1_{init,final}Emil Velikov2017-03-152-15/+15
| | | | | | | | | | | | Rather than having an extra memory allocation [that we currently do not and act accordingly] just make the API take an pointer to a stack allocated instance. This and follow-up steps will effectively make the _mesa_sha1_foo simple define/inlines around their SHA1 counterparts. Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Grazvydas Ignotas <[email protected]>
* radv: Remove unused descriptor set field.Bas Nieuwenhuizen2017-03-151-1/+0
| | | | | | Trivial. Signed-off-by: Bas Nieuwenhuizen <[email protected]>
* radv: trivial tidy upsTimothy Arceri2017-03-152-5/+2
| | | | Reviewed-by: Edward O'Callaghan <[email protected]>
* radv: Set driver version to mesa version;Bas Nieuwenhuizen2017-03-151-1/+23
| | | | | | | | | | | | | I couldn't really find an encoding in the spec. I'm not sure it prescribes VK_MAKE_VERSION format, but vulkan.gpuinfo.org interprets it that way by default. vulkaninfo gives the raw number, so we could alternatively do something like 17001000, but that doesn't show up right on vulkan.gpuinfo.org again. Looking at that site, the -pro driver also uses VK_MAKE_VERSION, so keeping consistency is probably best. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Acked-by: Dave Airlie <[email protected]>
* radv: Increase api version to 1.0.42.Bas Nieuwenhuizen2017-03-151-1/+1
| | | | | | | | | I've skimmed to changes from 1.0.5 to 1.0.42 and I think we have all changes. We're still not conformant ofcourse, but this should not regress stuff, Signed-off-by: Bas Nieuwenhuizen <[email protected]> Acked-by: Dave Airlie <[email protected]>
* radv: Flush before copying with PKT3_WRITE_DATA in CmdUpdateBufferAlex Smith2017-03-141-0/+2
| | | | | | | | | | | | | | | Need to flush before updating the buffer to ensure that the copy is ordered after previous accesses (assuming the app has performed the appropriate barriers). This fixes potential issues due to draws prior to an update reading the new buffer content, despite having the necessary barriers between them. Signed-off-by: Alex Smith <[email protected]> Cc: 17.0 <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: Emit cache flushes before CP DMA.Bas Nieuwenhuizen2017-03-141-0/+3
| | | | | | | | The flushes could be due to TRANSFER barriers. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Cc: 17.0 <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* nir: Rework conversion opcodesJason Ekstrand2017-03-141-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | The NIR story on conversion opcodes is a mess. We've had way too many of them, naming is inconsistent, and which ones have explicit sizes was sort-of random. This commit re-organizes things and makes them all consistent: - All non-bool conversion opcodes now have the explicit size in the destination and are named <src_type>2<dst_type><size>. - Integer <-> integer conversion opcodes now only come in i2i and u2u forms (i2u and u2i have been removed) since the only difference between the different integer conversions is whether or not they sign-extend when up-converting. - Boolean conversion opcodes all have the explicit size on the bool and are named <src_type>2<dst_type>. Making things consistent also allows nir_type_conversion_op to be moved to nir_opcodes.c and auto-generated using mako. This will make adding int8, int16, and float16 versions much easier when the time comes. Reviewed-by: Eric Anholt <[email protected]>
* radv: Reinitialise loaderMagic when allocating a cached command bufferAlex Smith2017-03-131-0/+1
| | | | | | | | | | | This must be set to ICD_LOADER_MAGIC by vkAllocateCommandBuffers, which was being done when allocating a new buffer but not when reusing an existing one in the cache. This would hit an assertion and crash in debug builds of the Vulkan loader. Fixes: 682248db451f ("radv: Cache command buffers in command pool.") Signed-off-by: Alex Smith <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* vulkan/wsi: Generate wayland protocol headers separately from EGLJason Ekstrand2017-03-131-3/+0
| | | | | | | | | | | | | | | | Previously, we were depending on EGL for generating the headers and providing the protocol symbols. However, since neither Vulkan driver actually wants to link against EGL, this is kind of pointless. It also creates a weird build dependency. v2 [Jason] - Add missing wsi/ prefix, MKDIR_GEN v3 [Emil Velikov] - include BUILT_SOURCES/generation rules outside of conditional Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* radv/wsi: Don't include wayland headersEmil Velikov2017-03-131-3/+0
| | | | | | | | | Unused and we'll rework the way wayland-drm-client-protocol.h is generated with later commit. Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Acked-by: Dave Airlie <[email protected]>
* radv: Store shaders in VRAM.Bas Nieuwenhuizen2017-03-132-2/+2
| | | | | | | | | | Less IFETCH latency on misses. Shader code is write once read many, so GTT doesn't make much sense anyway. If it turns out to fragment the CPU visible VRAM too much, we can upload with SDMA. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: disabled scaled formats for transfers.Dave Airlie2017-03-131-7/+10
| | | | | | | These really are only supported for vertex buffers. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* amd: remove shebang from python scriptsEmil Velikov2017-03-102-2/+0
| | | | | | | Analogous to earlier commit(s). Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Eric Engestrom <[email protected]>
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