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* radv: Save descriptor set even if vertex buffers are not saved.Bas Nieuwenhuizen2017-05-131-2/+3
| | | | | | | | Totally independent. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]> Fixes: 0e6d532d327 "radv/meta: add support for save/restore meta without vertex data."
* radv: handle fragment shader srgb resolve pass betterDave Airlie2017-05-112-11/+38
| | | | | | | | | | | Bas pointed out the fs key doesn't take srgb into account, since there is just one srgb variant, just create a separate pipeline for it. This also uses dest format to be more consistent on when srgb matters. Fixes: 69136f4e633 "radv/meta: add resolve pass using fragment/vertex shaders" Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: always free nir shaders from modules on stackGrazvydas Ignotas2017-05-102-8/+4
| | | | | | | | | valgrind reports them as leaked, and I could not find anything making a copy of the nir pointer. Also, radv_device_init_meta_blit_color() is already freeing them unconditionally like this. Signed-off-by: Grazvydas Ignotas <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* nir: Embed the shader_info in the nir_shader againJason Ekstrand2017-05-0911-92/+92
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit e1af20f18a86f52a9640faf2d4ff8a71b0a4fa9b changed the shader_info from being embedded into being just a pointer. The idea was that sharing the shader_info between NIR and GLSL would be easier if it were a pointer pointing to the same shader_info struct. This, however, has caused a few problems: 1) There are many things which generate NIR without GLSL. This means we have to support both NIR shaders which come from GLSL and ones that don't and need to have an info elsewhere. 2) The solution to (1) raises all sorts of ownership issues which have to be resolved with ralloc_parent checks. 3) Ever since 00620782c92100d77c660f9783504c6d80fa1d58, we've been using nir_gather_info to fill out the final shader_info. Thanks to cloning and the above ownership issues, the nir_shader::info may not point back to the gl_shader anymore and so we have to do a copy of the shader_info from NIR back to GLSL anyway. All of these issues go away if we just embed the shader_info in the nir_shader. There's a little downside of having to copy it back after calling nir_gather_info but, as explained above, we have to do that anyway. Acked-by: Timothy Arceri <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* radv: fix regression in blit2d push constant change.Dave Airlie2017-05-081-1/+1
| | | | | | | | | These were being fed to the shader as floats via the vertex path, so also push them as floats here. This fixes missing overlay in Sascha Willems demos. Signed-off-by: Dave Airlie <[email protected]>
* radv/meta: cleanup some unused code pathDave Airlie2017-05-082-34/+1
| | | | | | | | After moving everything to using push constants, these paths are no longer needed. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv/meta: port blit to using push constantsDave Airlie2017-05-081-100/+65
| | | | | | | Remove use of vertex buffer. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv/meta: move blit2d to using push constantsDave Airlie2017-05-082-75/+59
| | | | | | | This allows us to drop the vertex buffer. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv/meta: move clear color to using push constantsDave Airlie2017-05-082-130/+78
| | | | | | | | | | | | The color clear value is uniform and needs only to be emitted from the frag shader, so just push it down via a push constant, and remove the vertex buffer completely. The depth clear value needs to be emitted from the vertex shader, but is only a single value. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv/meta: use novertex save path for resolve pass.Dave Airlie2017-05-082-2/+2
| | | | | | | This was missing in the original change. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: set base/ranges for push constant loads.Dave Airlie2017-05-086-0/+26
| | | | | | | | | This isn't necessary yet but I'd like to use the range in some future patches. [airlied: add new resolve pass] Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: drop resolve hack workaroundsDave Airlie2017-05-073-104/+1
| | | | | | | | | This drops the resolve workarounds that change an image tiling mode behinds it's back, this is horrible and breaks the image_view->image relationship. Remove all this. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv/meta: select resolve pathsDave Airlie2017-05-071-8/+50
| | | | | | | | | | | | | | | | There are 3 resolve paths, the fastest being the hw resolver but it has restriction on tile modes and can't do subresolves, the compute resolver is next speed wise, but can't handle DCC destinations, the fragment resolver handles that case. This will end up with a slow down as currently we hack the hw resolver paths when they shouldn't work, but we shouldn't keep doing that. The next patch removes the hacks. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv/meta: add resolve pass using fragment/vertex shadersDave Airlie2017-05-076-2/+699
| | | | | | | | | | | In order to resolve into DCC enabled dests we need to use the fragment shader. This reuses the code from the compute path and implements a resolve path in vertex/fragment shader. This code isn't used until later. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: add subpass resolve compute pathDave Airlie2017-05-072-0/+94
| | | | | | | | | | This adds a path to allow compute resolves to be used for subpass resolves. This isn't used yet, but will be later. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv/resolve: split resolve emission out for computeDave Airlie2017-05-071-63/+78
| | | | | | | This will allow to add a subpass compute resolve path. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv/meta: split out core part of resolve shaderDave Airlie2017-05-073-113/+140
| | | | | | | | I want to reuse the same code for the fragment shader version of the resolve shaders. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv/meta: add srgb conversion to end of resolve shader.Dave Airlie2017-05-073-5/+61
| | | | | | | | | | | If we are resolving into an srgb dest, we need to convert to linear so the store does the conversion back. This should fix some wierdness seen when we subresolves hit the compute path. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: set PERF_MOD in sample state like radeonsi.Dave Airlie2017-05-071-1/+2
| | | | | | | This just aligns the code with radeonsi. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: apply the tess+GS hang workaround to Polaris12 as wellDave Airlie2017-05-071-1/+2
| | | | | | | | | As I pointed out for radeonsi, and AMD confirmed, so fix this in radv as well. Cc: "17.1" <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv/meta: fix restoring a push descriptor setFredrik Höglund2017-05-062-2/+7
| | | | | | | | | | | radv_bind_descriptor_set cannot be used to bind a push descriptor set since a push descriptor set does not have a buffer list. However, there is no need to add the buffers again when restoring a set, so this fix is also an optimization. Cc: "17.1" <[email protected]> Signed-off-by: Fredrik Höglund <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: enable POLARIS12 support.Dave Airlie2017-05-053-0/+7
| | | | | | | | | | | This just adds the chip in the right places. We don't set the partial_vs_wave workaround, as radeonsi doesn't, but have to confirm it's not required. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Cc: "17.1" <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: don't advertise transfer props unless we can do anything elseDave Airlie2017-05-051-2/+2
| | | | | | | | | There is no reason to advertise transfer ability for formats we can't use for anything else. This stops some CTS tests hitting internal error for 64-bit types when they see the transfer flags. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: Don't use FLAT_SHADE for constants.Bas Nieuwenhuizen2017-05-041-4/+4
| | | | | | | | | Setting both offset to 0x20 and flat shade results in passthrough mode instead of the constant. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]> Fixes: f205e19e4f8 "radv/ac: eliminate unused vertex shader outputs. (v2)"
* radv: don't leak DRM devicesGrazvydas Ignotas2017-05-031-1/+3
| | | | | | | | After successful drmGetDevices2() call, drmFreeDevices() needs to be called. Fixes: 743315f2 "radv: do not open random render node(s)" Signed-off-by: Grazvydas Ignotas <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: fix possible stack corruptionGrazvydas Ignotas2017-05-031-1/+1
| | | | | | | | | | drmGetDevices2 takes count and not size. Probably hasn't caused problems yet in practice and was missed as setups with more than 8 DRM devices are not very common. Fixes: 743315f2 "radv: do not open random render node(s)" Signed-off-by: Grazvydas Ignotas <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: Add userspace fence buffer per context.Bas Nieuwenhuizen2017-05-034-37/+44
| | | | | | | | | | Having it in the winsys didn't work when multiple devices use the same winsys, as we then have multiple contexts per queue, and each context counts separately. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]> Fixes: 7b9963a28f4 "radv: Enable userspace fence checking."
* radv: enable lower_sub to fix loop unrolling.Dave Airlie2017-05-031-0/+1
| | | | | | | | | | Loop unroll asserts if it hits a sub, we don't really want to lower subs as llvm handles these things, but do this for now, until we can fix loop unroll to work with subs. Fixes: 14ae0bfa5 (radv: Add NIR loop unrolling) Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: Don't set dynamic state for pipelines with rasterizer dicard.Bas Nieuwenhuizen2017-05-031-6/+9
| | | | | | | | | | | | All of the dynamic states apply to rasterization & fragment processing, so we don't need to set them if we don't rasterize. We don't clear the dirty flags for them though, so we don't miss any updates for the next pipeline with rasterization. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]> Fixes: 76603aa90b8 "radv: Drop the default viewport when 0 viewports are given."
* radv: flush more stages when semaphore are waiting.Dave Airlie2017-05-032-3/+23
| | | | | | | | | | | | | | | This still doesn't give us complete pWaitDstStageMask support, but it should provide enough to be correct if not as efficent as possible. If we have wait semaphores we must flush between submits and flush the shaders as well. This fixes the remaining fails in: dEQP-VK.synchronization.op.single_queue.semaphore.*ssbo* Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: fix stencil only clears.Dave Airlie2017-05-031-0/+3
| | | | | | | | | | | | | | | If we are clearing stencil only, we still need to provide a a valid Z output from the vertex shader, we can't rely on the depth clear value having any meaning, as we use this for the position output, and it could get clipped, so we don't end up clearing anything. Fixes: dEQP-VK.renderpass.simple.stencil since I added S8 support. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv/wsi: report presentation error per image requestDave Airlie2017-05-031-6/+13
| | | | | | | | | | | | This ports 0fcb92c17dee681bd39c08ddf0abc358a27337c7 anv: wsi: report presentation error per image request This fixes: dEQP-VK.wsi.xlib.incremental_present.scale_none.* Reviewed-by: Daniel Stone <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: minor pahole related improvements.Dave Airlie2017-05-033-5/+5
| | | | | | | This just reduces the structs by 4-8 bytes each. Reviewed-by: Timothy Arceri <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv/image: resize some surface members.Dave Airlie2017-05-031-3/+3
| | | | | | | Oops meant to be part of previous series. Reviewed-by: Timothy Arceri <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: drop unused surface level members.Dave Airlie2017-05-032-6/+0
| | | | | Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv/image: drop blk_dDave Airlie2017-05-033-3/+1
| | | | | | | This was pretty much unused. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: remove some members of radeon surface.Dave Airlie2017-05-034-48/+40
| | | | | | | | We would be storing this info twice per image, no need to, remove it from the surface struct. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: move some image info into a separate struct.Dave Airlie2017-05-0313-80/+90
| | | | | | | This is to rework the surface code like radeonsi. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: provide a helper for comparing an image extents.Dave Airlie2017-05-032-2/+11
| | | | | | | | This just makes it easier to do the follow in cleanups of the surface. Reviewed-by: Timothy Arceri <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: Use correct stage for ready bit.Bas Nieuwenhuizen2017-05-021-9/+24
| | | | | | | | Set the bit in the same stage as the timestamp, instead always at top of pipe. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]> Tested-by: Grazvydas Ignotas <[email protected]>
* radv: Add top of pipe timestamp queries.Bas Nieuwenhuizen2017-05-021-12/+26
| | | | | | | Does not fix brokenness with the ready bit. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: Add NIR loop unrolling.Bas Nieuwenhuizen2017-05-021-0/+10
| | | | | | | | Not much effect on dota2/talos, but positive on deferred. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Timothy Arceri <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv/ac: eliminate unused vertex shader outputs. (v2)Dave Airlie2017-04-271-7/+8
| | | | | | | | | | | This is ported from radeonsi, and I can see at least one Talos shader drops an export due to this, and saves some VGPR usage. v2: use shared code. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: fix regression in descriptor set freeing.Dave Airlie2017-04-271-1/+1
| | | | | | | | | | | Since the host pool changes, Fixes: dEQP-VK.api.descriptor_pool.out_of_pool_memory Fixes: 126d5ad "radv: Use host memory pool for non-freeable descriptors." Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: Enable userspace fence checking.Bas Nieuwenhuizen2017-04-263-3/+36
| | | | | | | | | | v2: - Added some error handling. - memset the buffer to 0. v3: Added assert for buffer size. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv/ac: overhaul vs output/ps input routingDave Airlie2017-04-251-31/+36
| | | | | | | | In order to cleanly eliminate exports rewrite the code first to mirror how radeonsi works for now. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv/ac: move point coord after layer/viewport.Dave Airlie2017-04-251-6/+7
| | | | | | | | These need to be ordered as per shader enum ordering, I'll rewrite this soon, but this is a bug fix. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: Enable lowering fdiv in nir.Bas Nieuwenhuizen2017-04-231-0/+1
| | | | | | | Results in faster code than the lowering by LLVM. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: Use the correct pipeline for dispatches.Bas Nieuwenhuizen2017-04-221-3/+3
| | | | | | | Signed-off-by: Bas Nieuwenhuizen <[email protected]> Fixes: ec15e0d30 "radv: optimise compute shader grid size emission." Tested-by: Grazvydas Ignotas <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: Prefetch compute shader too.Bas Nieuwenhuizen2017-04-211-0/+1
| | | | | | | For consistency, doesn't really impact performance. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
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