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* radv: Increase descriptor limits.Bas Nieuwenhuizen2017-04-041-14/+14
| | | | | | | | We supported more generally. Decreased the dynamic buffers though, as we only support 16 for uniform+storage. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Acked-by: Dave Airlie <[email protected]>
* radv: Rework guard band calculation.Bas Nieuwenhuizen2017-04-031-40/+15
| | | | | | | | | | | | | | | | | | We want the guardband_x/y to be the largerst scalars such that each viewport scaled by that amount is still a subrange of [-32767, 32767]. The old code has a couple of issues: 1) It used scissor instead of viewport_scissor, potentially taking into account a viewport that is too small and therefore selecting a scale that is too large. 2) Merging the viewports isn't ideal, as for example viewports with boundaries [0,1] and [1000, 1001] would allow a guardband scale of ~30k, while their union [0, 1001] only allows a scale of ~32. The new code just determines the guardband per viewport and takes the minimum. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Acked-by: Dave Airlie <[email protected]>
* radv: Enable VK_KHR_incremental_present.Bas Nieuwenhuizen2017-04-033-1/+15
| | | | | | | Just enabling the driver-independent implementation that Jason did. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* vulkan/wsi: Plumb present regions through the common codeJason Ekstrand2017-04-031-1/+2
| | | | | | Reviewed-by: Lionel Landwerlin <[email protected]> Reviewed-by: Daniel Stone <[email protected]> Acked-by: Dave Airlie <[email protected]>
* radv: overhaul fragment shader sample positions.Dave Airlie2017-04-043-36/+67
| | | | | | | | | | | | | | | | | | The current code was broken, and I decided to redesign it instead. This puts the sample positions for all samples into the queue constant descriptor buffer after all the spill/ring descriptors. It then uses a single offset register to point how far into the samples the samples for num_samples are. This saves one user sgpr and means we only generate the sample position data in the rare single case where we need it currently. This doesn't fix the failing CTS tests without the followup fix. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: fix order of the guardband register emission.Dave Airlie2017-04-021-2/+2
| | | | | | | | | y is vert, x is horiz. Noticed in visual inspection compared to radeonsi. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: enable tessellation shaders.Dave Airlie2017-04-012-9/+10
| | | | | | | | This enables tessellation shaders and sets some values for the maximums. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: add ia_multi_vgt_param tessellation support.Dave Airlie2017-04-011-2/+30
| | | | | | | This just ports the relevant radeonsi pieces. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv/cmd: emit tessellation state.Dave Airlie2017-04-011-4/+109
| | | | | | | | | This emits the tessellation shaders and state to the command stream. It contains the logic to emit the LS/HS shaders. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv/pipeline: handle tessellation shader compilationDave Airlie2017-04-011-0/+142
| | | | | | | | | | | | | | So tess shaders have some circular dependencies, TCS needs the TES primitive mode TES needs the TCS vertices out This builds the nir for each shader first to get the info, executes a tes specific nir pass, then builds the LLVM shaders. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv/pipeline: start calculating tess stage.Dave Airlie2017-04-012-9/+208
| | | | | | | | | | | This calculates the pipeline state for tessellation. It moves the gs ring calculation down to below where the tessellation shaders will be compiled, as it needs the info from those shaders. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: add tessellation support to variant code.Dave Airlie2017-04-011-6/+9
| | | | | | | This just fills out the rsrc registers for tess shaders. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: add tessellation support to shader namingDave Airlie2017-04-011-1/+3
| | | | | Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: port polaris vgt vertex reuse workaround.Dave Airlie2017-04-012-1/+18
| | | | | | | | This ports the VGT_VERTEX_REUSE register settings for Polaris GPUs from radeonsi. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: configure tessellation distribution register.Dave Airlie2017-04-011-4/+12
| | | | | | | This just takes the radeonsi values. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: add tessellation ring allocation support. (v2)Dave Airlie2017-04-013-13/+203
| | | | | | | | | | | | This patch adds support for the offchip rings for storing tessellation factors and attribute data. It includes the register setup for the TF ring v2: always do tess ring size calcs (Bas) Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: add support for some device specific tess information.Dave Airlie2017-04-012-0/+8
| | | | | Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: add tess shader stage user data support.Dave Airlie2017-04-011-7/+38
| | | | | | | | This just adds support for tess to the shader stage conversion and emits the per-stage descriptors/constants for tess stages. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: add helper function to denote if tess is enabled on a pipeline.Dave Airlie2017-04-011-0/+5
| | | | | Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: Use the guard band.Bas Nieuwenhuizen2017-03-303-13/+90
| | | | | Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: Prepare for not using the guard band for lines & points.Bas Nieuwenhuizen2017-03-303-0/+32
| | | | | | | | | | | Vulkan Clipping is defined in terms of vertices, the scissor based clipping happens on pixels. There is a difference with points and lines, as a vertex can be outside the viewport while some pixels are in. On Vulkan thoise pixels shouldn't be drawn, while they would be with the guardband. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: Drop the default viewport when 0 viewports are given.Bas Nieuwenhuizen2017-03-301-17/+2
| | | | | Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: Set proper viewport & scissor for meta draws.Bas Nieuwenhuizen2017-03-306-75/+214
| | | | | Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* amd: GFX9 packet changesMarek Olšák2017-03-301-2/+2
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* amd: add texture format definitions for GFX9Marek Olšák2017-03-301-4/+4
| | | | | | | | the DATA_FORMAT and NUM_FORMAT fields are the same, but some of the enums differ, thus add GFX6 and GFX9 suffixes, so that the IB parser can show enums for both. Reviewed-by: Nicolai Hähnle <[email protected]>
* amd: resolve remaining definition conflicts with gfx9d.hMarek Olšák2017-03-301-3/+3
| | | | | | | | Add _GFX6 and _GFX9 suffixes to conflicting definitions. sid.h and gfx9d.h can now be included in the same file. Reviewed-by: Nicolai Hähnle <[email protected]>
* amdgpu/addrlib: Rewrite tile mode optmization codeXavi Zhang2017-03-301-3/+2
| | | | Note: remove reference to degrade4Space and use opt4Space instead.
* radv: move to using nir clip/cull merge pass.Dave Airlie2017-03-301-0/+1
| | | | | | | | | | Doing this before tessellation makes doing some bits of tessellation a bit cleaner. It also cleans up a bit of the llvm generator code. Reviewed-by: Edward O'Callaghan <[email protected]> Acked-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: Enable sparseBinding feature.Bas Nieuwenhuizen2017-03-291-4/+8
| | | | | Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv/amdgpu: Use reference counting for bos.Bas Nieuwenhuizen2017-03-292-0/+11
| | | | | | | | | | | | | Per the Vulkan spec, memory objects may be deleted before the buffers and images using them are deleted, although those resources then cannot be used except for deletion themselves. For the virtual buffers, we need to access them on resource destruction to unmap the regions, so this results in a use-after-free. Implement reference counting to avoid this. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: Implement sparse memory binding.Bas Nieuwenhuizen2017-03-291-4/+80
| | | | | | | v2: Only submit when semaphores are specified. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: Implement sparse image creation.Bas Nieuwenhuizen2017-03-292-2/+22
| | | | | Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: Implement sparse buffer creation.Bas Nieuwenhuizen2017-03-292-2/+21
| | | | | Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv/amdgpu: Add winsys implementation of virtual buffers.Bas Nieuwenhuizen2017-03-294-26/+349
| | | | | | | | | v2: - Added comments. - Fixed a double unmap bug. - Actually unmap the non-edge old ranges. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: Assert when setting 0 registers in a sequence.Bas Nieuwenhuizen2017-03-291-0/+4
| | | | | | | To catch more of those hangs early. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Acked-by: Dave Airlie <[email protected]>
* radv: only emit ps_input_cntl is we have any to outputDave Airlie2017-03-281-3/+6
| | | | | | | Otherwise we get GPU hangs. Reported-by: Alex Smith <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: move shader stages calculation to pipeline.Dave Airlie2017-03-283-9/+10
| | | | | | | | With tess this becomes a bit more complex. so move to pipeline for now. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: move pa_cl_vs_out_cntl calculation to pipelineDave Airlie2017-03-283-17/+32
| | | | | | | This also takes the side band setting code from radeonsi. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: move calculating fragment shader i/os to pipeline.Dave Airlie2017-03-283-63/+77
| | | | | | | There is no need to calculate this on each command submit. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: move shader_z_format calculation to pipeline.Dave Airlie2017-03-283-4/+8
| | | | | | | No need to recalculate this every time. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: move db_shader_control calculation to pipeline.Dave Airlie2017-03-283-16/+20
| | | | | | | There is no need to recalculate this every time. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: move vgt_gs_mode value to pipeline.Dave Airlie2017-03-283-27/+30
| | | | | | | No need to recalculate this everytime. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: rework vertex/export shader output handlingDave Airlie2017-03-282-33/+39
| | | | | | | | | In order to faciliate adding tess support, split the vs/es output info into a separate block, so we make it easier to have the tess shaders export the same info. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: fix ia_multi_vgt_param for instanced vs indirect draw.Dave Airlie2017-03-283-13/+15
| | | | | | | | The logic was different than radeonsi, fix it up before adding tess support. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: handle NULL multisample state.Dave Airlie2017-03-281-8/+12
| | | | | | | | If rasterization is disabled, we can get a NULL multisample state. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: flush DB cache before and after HTILE decompress.Bas Nieuwenhuizen2017-03-281-0/+6
| | | | | | | | | | | It reads @ writes the DB cache, and we haven't flushed dst caches yet, so DB cache may be stale. Also the user might be shader read (and probably is), so also flush after. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]> CC: <[email protected]> Fixes: f4e499ec791 ("radv: add initial non-conformant radv vulkan driver")
* radv: don't emit no color formats. (v3)Dave Airlie2017-03-281-2/+19
| | | | | | | | | | | | | | | If we had no rasterization, we'd emit SPI color format as all 0's the hw dislikes this, add the workaround from radeonsi. Found while debugging tessellation v2: handle at pipeline stage, we have to handle it after we process the fragment shader. (Bas) v3: simplify even further, remove old fallback. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: Invalidate L2 for TRANSFER_WRITE barriersAlex Smith2017-03-231-1/+1
| | | | | | | | | | | | CP DMA and PKT3_WRITE_DATA (in CmdUpdateBuffer) don't (currently) write through L2. Therefore, to make these writes visible to later accesses we must invalidate L2 rather than just writing it back, to avoid the possibility that stale data is read through L2. Cc: "17.0" <[email protected]> Signed-off-by: Alex Smith <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: consistently use ifndef guards over pragma onceEmil Velikov2017-03-221-1/+4
| | | | | | | | | | Namely: annotate the single file which is not using a ifndef guard - vk_format.h Signed-off-by: Emil Velikov <[email protected]> Acked-by: Vedran Miletić <[email protected]> Acked-by: Juha-Pekka Heikkila <[email protected]> Reviewed-by: Edward O'Callaghan <[email protected]>
* radv: move KHR_get_physical_device_properties2 to instance props.Dave Airlie2017-03-211-4/+4
| | | | | | | | | This is an instance property not a device one. Fixes: dEQP-VK.api.info.device.extensions Signed-off-by: Dave Airlie <[email protected]>
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