summaryrefslogtreecommitdiffstats
path: root/src/amd/vulkan
Commit message (Expand)AuthorAgeFilesLines
...
* radv: fix VGT_ESGS_RING_ITEMSIZE for GS as NGG on GFX10Samuel Pitoiset2019-07-091-2/+7
* radv: emit VGT_GS_MAX_VERT_OUT for legacy and NGG paths for GSSamuel Pitoiset2019-07-091-2/+3
* radv: emit the geometry shader as NGG if enabled on GFX10Samuel Pitoiset2019-07-091-3/+7
* radv: keep track of whether NGG is used for GS on GFX10Samuel Pitoiset2019-07-093-1/+10
* radv: add radv_pipeline_generate_hw_gs() helperSamuel Pitoiset2019-07-091-9/+20
* radv: fix setting VGT_REUSE_OFF for TES on GFX10Samuel Pitoiset2019-07-091-2/+7
* radv: fix computing the number of ES VGPRS for TES on GFX10Samuel Pitoiset2019-07-091-1/+2
* radv: set max workgroup size to 128 for TES as NGG on GFX10Samuel Pitoiset2019-07-091-1/+1
* radv: fix allocating USER SGPRs on GFX10Samuel Pitoiset2019-07-091-7/+8
* radv/gfx10: Enable tess.Bas Nieuwenhuizen2019-07-091-1/+1
* radv/gfx10: Add pipeline state support for tess.Bas Nieuwenhuizen2019-07-092-10/+45
* radv/gfx10: Only set HW edge flags with gs & tess disabled.Bas Nieuwenhuizen2019-07-091-1/+2
* radv/gfx10: Add tess eval ngg shader support.Bas Nieuwenhuizen2019-07-091-8/+17
* radv: Use correct gs_out with tessellation.Bas Nieuwenhuizen2019-07-091-0/+3
* radv/gfx10: Use correct count of max_offchip_buffers.Bas Nieuwenhuizen2019-07-091-1/+4
* radv/gfx10: Load global pointers in correct userdata registers for hs/gs.Bas Nieuwenhuizen2019-07-091-2/+2
* radv: only use specialised 3D meta paths on GFX9.Dave Airlie2019-07-092-16/+16
* radv: do not emit VGT_FLUSH on GFX10Samuel Pitoiset2019-07-081-2/+5
* radv: Use NIR barycentric intrinsicsConnor Abbott2019-07-083-191/+156
* radv: Make FragCoord a sysvalConnor Abbott2019-07-083-17/+4
* radv: Lower input attachments in NIR.Daniel Schürmann2019-07-085-12/+4
* radv: Implement nir_intrinsic_load_layer_id().Daniel Schürmann2019-07-082-1/+6
* radv/gfx10: don't emit PFP packets on ME.Dave Airlie2019-07-081-2/+3
* ac: select the GFX ring when halting waves with UMR on GFX10Samuel Pitoiset2019-07-081-1/+2
* radv/gfx10: Move NGG output handling outside of giant if-statement.Bas Nieuwenhuizen2019-07-081-2/+10
* radv: Actually use VK formats for the format table.Bas Nieuwenhuizen2019-07-071-48/+20
* radv: Handle cmask being disallowed by addrlib.Bas Nieuwenhuizen2019-07-071-0/+5
* radv/gfx10: enable support for NAVI10, NAVI12 and NAVI14Samuel Pitoiset2019-07-071-3/+0
* radv/gfx10: Use GS rectlist when needed.Bas Nieuwenhuizen2019-07-071-0/+2
* radv/gfx10: implement NGG support (VS only)Samuel Pitoiset2019-07-076-22/+610
* radv: Combine vs and tes output keys parts.Bas Nieuwenhuizen2019-07-074-46/+48
* radv/gfx10: Use new uconfig reg index packet for GFX10+.Bas Nieuwenhuizen2019-07-074-6/+18
* radv/gfx10: Set MEM_ORDERED flags on shaders.Bas Nieuwenhuizen2019-07-071-0/+9
* radv/gfx10: emit GE_CNTL instead of IA_MULTI_VGT_PARAM for legacy modeSamuel Pitoiset2019-07-072-4/+44
* radv/gfx10: double the number of tessellation offchip buffers per SESamuel Pitoiset2019-07-071-3/+5
* radv/gfx10: require LLVM 9+Samuel Pitoiset2019-07-071-0/+6
* radv/gfx10: disable geometry and tessellation shadersSamuel Pitoiset2019-07-071-2/+2
* radv/gfx10: disable binningSamuel Pitoiset2019-07-071-1/+2
* radv/gfx10: disable CLEAR_STATESamuel Pitoiset2019-07-072-5/+2
* radv/gfx10: disable VK_EXT_transform_feedbackSamuel Pitoiset2019-07-071-1/+1
* radv/gfx10: set user data base registersSamuel Pitoiset2019-07-071-17/+26
* radv/gfx10: add gfx10_cs_emit_cache_flushSamuel Pitoiset2019-07-071-1/+174
* radv/gfx10: set the DCC constant encoding flagSamuel Pitoiset2019-07-071-1/+2
* radv/gfx10: do not declare streamout SGPRSSamuel Pitoiset2019-07-071-0/+3
* radv/gfx10: do not set stream output shader configSamuel Pitoiset2019-07-071-7/+7
* radv/gfx10: emit VGT_VERTEX_REUSE_BLOCK_CNTL during gfx initializationSamuel Pitoiset2019-07-072-1/+3
* radv/gfx10: update shader-related fields in si_emit_graphics()Samuel Pitoiset2019-07-071-0/+13
* radv/gfx10: implement si_emit_compute()Samuel Pitoiset2019-07-071-1/+5
* radv/gfx10: mask DCC tile swizzle by alignmentSamuel Pitoiset2019-07-071-1/+4
* radv/gfx10: initialize GE_{MAX,MIN}_VTX_INDX/INDX_OFFSETSamuel Pitoiset2019-07-071-1/+5
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-20 16:15:34 +0000