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* radv: remove the temp descriptor set infrastructureFredrik Höglund2017-04-142-76/+28
| | | | | | | It is no longer used. Signed-off-by: Fredrik Höglund <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: use push descriptors in metaFredrik Höglund2017-04-146-416/+301
| | | | | | | Use push descriptors instead of temp descriptor sets. Signed-off-by: Fredrik Höglund <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: add private push descriptors for metaFredrik Höglund2017-04-142-0/+41
| | | | | | | | | | | | This allows meta to use push descriptors without disturbing user push descriptors. radv_meta_push_descriptor_set differs from vkCmdPushDescriptorSetKHR in that partial updates are not supported; all descriptors used in subsequent draw commands must be pushed at the same time. Signed-off-by: Fredrik Höglund <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: remove irrelevant commentGrazvydas Ignotas2017-04-141-1/+1
| | | | | | | A leftover from anv. Signed-off-by: Grazvydas Ignotas <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: report timestampPeriod correctlyGrazvydas Ignotas2017-04-142-2/+2
| | | | | | | | | | | | The kernel returns frequency in kHz, so to convert to nanosecond interval that Vulkan uses the dividend should be 1000000.0 and not 100000.0. This fixes the GPU graph in DOOM and matches the amdgpu-pro blob. Fixes: f4e499ec791 "radv: add initial non-conformant radv vulkan driver" Signed-off-by: Grazvydas Ignotas <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: make sizes & offsets 32 bit in radv_descriptor_update_template_entry.Bas Nieuwenhuizen2017-04-142-7/+7
| | | | | | | v2: Also convert the calculations. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Fredrik Höglund <[email protected]>
* radv: Set descriptor set limits.Bas Nieuwenhuizen2017-04-131-15/+29
| | | | | | | Properly and with comments this time. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: Increase integer sizes in descriptor sets.Bas Nieuwenhuizen2017-04-131-8/+8
| | | | | | | | Needed if we want to allow them taking more than 64 KiB. The calculations of these already used 32 bits. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: support S8_UINT as a depth/stencil format.Dave Airlie2017-04-141-1/+1
| | | | | | | This enables a bunch of NotSupported CTS tests. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: bump maxGeometryShaderInvocations.Dave Airlie2017-04-141-1/+1
| | | | | | | | | This bumps it to the same level as amdgpu-pro, it also moves a bunch of dEQP-VK.geometry.instanced.* from NotSupported to Pass. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: Add more trace points.Bas Nieuwenhuizen2017-04-132-0/+3
| | | | | | | | | | | Most trace points happen after an operation, so add a trace point at the start of the command buffer. Furthermore, add one after a CmdUpdateBuffer using CP_DMA as that didn't emit one yet. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: Ignore CmdUpdateBuffer with size 0.Bas Nieuwenhuizen2017-04-131-0/+3
| | | | | Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: Enable query inheritance.Bas Nieuwenhuizen2017-04-131-1/+1
| | | | | | | | | | | | | | timestamp and pipeline_statistics only do something on begin & end, so they don't need any action. Occlusion queries only do something to enable/disable and that register is set nowhere else so that doesn't need extra support either. (We technically should fix it to update the reg with the number of samples, but that hasn't happened yet, so we only change it to enable/disable counting) Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: enable variableMultisampleRate.Bas Nieuwenhuizen2017-04-131-1/+1
| | | | | | | | | This is only relevant with 0 attachments. In that case we do nothing on subpass switch already, and the pipeline is the authoritative source of the number of samples, so this shouldn't change anything. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: fix stencil regression since new addrlib importDave Airlie2017-04-132-1/+9
| | | | | | | | | | The addrlib import meant we'd return after we attempted to setup the no stencil bits for an S8_UINT, now we break and use the stencil level info when creating stencil DB info. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: allocate thin textures as linear.Dave Airlie2017-04-131-0/+7
| | | | | | | | | | This is ported from radeonsi, and avoids the bug in the addrlib code. This should probably be something addrlib does for us, but for now this fixes the regression without changing addrlib and aligns us with radeonsi. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: Disable primitive restart for non-indexed drawsAlex Smith2017-04-122-22/+34
| | | | | | | | | | | | | | | | According to the Vulkan spec, VkPipelineInputAssemblyStateCreateInfo's primitiveRestartEnable flag should only apply to indexed draws, however it was being enabled regardless of the type of draw. This could cause problems for non-indexed draws with >=65535 vertices if the previous indexed draw used 16-bit indices. Fixes corruption of the credits text in Mad Max. v2: Reset primitive restart state after executing a secondary command buffer. Signed-off-by: Alex Smith <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: Hash the immutable samplers.Bas Nieuwenhuizen2017-04-121-0/+3
| | | | | | | Since the shader code can include them. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: Use an offset instead of pointers for immutable samplers.Bas Nieuwenhuizen2017-04-123-22/+32
| | | | | | | Makes more sense when we hash the layout for the pipeline cache. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: Stop shadowing the result in radv_GetQueryPoolResults.Bas Nieuwenhuizen2017-04-121-4/+4
| | | | | | | The outer result was referred to, which meant bugs. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: Return VK_NOT_READY if the query results are not available.Bas Nieuwenhuizen2017-04-121-0/+6
| | | | | | Signed-off-by: Bas Nieuwenhuizen <[email protected]> Fixes: 8475a14302e ("radv: Implement pipeline statistics queries.") Reviewed-by: Fredrik Höglund <[email protected]>
* radv: Set query availability bit even if we don't wait.Bas Nieuwenhuizen2017-04-121-3/+4
| | | | | | Signed-off-by: Bas Nieuwenhuizen <[email protected]> Fixes: 8475a14302e ("radv: Implement pipeline statistics queries.") Reviewed-by: Fredrik Höglund <[email protected]>
* radv: Implement pipeline statistics queries.Bas Nieuwenhuizen2017-04-113-27/+394
| | | | | | | | | | | The devil is in the shader again, otherwise this is fairly straightforward. The CTS contains no pipeline statistics copy to buffer testcases, so I did a basic smoketest. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: Let count be dynamic in radv_break_on_count.Bas Nieuwenhuizen2017-04-111-3/+3
| | | | | Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: Rename query pipeline/set layout.Bas Nieuwenhuizen2017-04-112-13/+13
| | | | | | | For using them with both occlusion and pipeline statistics queries. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: Use VK_WHOLE_SIZE for the query buffer bindings.Bas Nieuwenhuizen2017-04-111-2/+2
| | | | | | | | The buffer sizes are specified just a few lines earlier, so don't repeat ourselves. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: Use a shader for occlusion CmdCopyQueryPoolResults.Bas Nieuwenhuizen2017-04-111-74/+64
| | | | | | | | | | | | | | | | | | Use the new occlusion query copy shader. We don't use the shader for the waiting as a polling loop ineracts badly with having caching enabled. I noticed on my GPU (Tonga) that the values are written out in order, so I just use a WAIT_REG_MEM on the last value. If it turns out other chips don't do that we may need to look a bit more into this. Having 8 WAIT_REG_MEM packets per query doesn't sound ideal. This also restricts the availability word in the pool to timestamp queries only, as occlusion queries don't use it, and pipeline statistic queries likely won't either. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: Add occlusion query shader.Bas Nieuwenhuizen2017-04-114-0/+435
| | | | | | | | | Adds a shader for writing occlusion query results to a buffer, as the CP packet isn't support on SI or secondary buffers, and doesn't handle the availability bit (or partial results) nor truncation to 32-bit. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: don't call radeon_check_space in radv_BindDescriptorSetsFredrik Höglund2017-04-071-5/+0
| | | | | | | | This appears to be a leftover from an earlier version of this function. Nothing is emitted into the CS. Signed-off-by: Fredrik Höglund <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: implement VK_KHR_descriptor_update_templateFredrik Höglund2017-04-075-0/+231
| | | | | | | | | | | All offsets and strides are precomputed by radv_CreateDescriptorUpdateTemplateKHR and stored in the template. v2: Move the new struct declarations from radv_descriptor_set.h to radv_private.h (Bas) Signed-off-by: Fredrik Höglund <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: implement VK_KHR_push_descriptorFredrik Höglund2017-04-076-2/+128
| | | | | Signed-off-by: Fredrik Höglund <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: replace an assertion with a conditionalFredrik Höglund2017-04-071-3/+3
| | | | | | | | | | | | | | | | Replace the !binding_layout->immutable_samplers assertion in radv_update_descriptor_sets with a conditional. The Vulkan specification does not say that it is illegal to update a sampler descriptor when it is immutable; only that pImageInfo is ignored. This change is also needed for push descriptors, because valid descriptors must be pushed for all bindings accessed by shaders, including immutable sampler descriptors. Signed-off-by: Fredrik Höglund <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: refactor radv_UpdateDescriptorSetsFredrik Höglund2017-04-072-12/+52
| | | | | | | | | | | | | Move the implementation into a separate function that takes a cmd_buffer and a dstSetOverride parameter. When cmd_buffer is not NULL, radv_update_descriptor_sets calls cs_add_buffer directly instead of updating the buffer list. This will be used to implement VK_KHR_push_descriptor. Signed-off-by: Fredrik Höglund <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: Increase descriptor limits.Bas Nieuwenhuizen2017-04-041-14/+14
| | | | | | | | We supported more generally. Decreased the dynamic buffers though, as we only support 16 for uniform+storage. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Acked-by: Dave Airlie <[email protected]>
* radv: Rework guard band calculation.Bas Nieuwenhuizen2017-04-031-40/+15
| | | | | | | | | | | | | | | | | | We want the guardband_x/y to be the largerst scalars such that each viewport scaled by that amount is still a subrange of [-32767, 32767]. The old code has a couple of issues: 1) It used scissor instead of viewport_scissor, potentially taking into account a viewport that is too small and therefore selecting a scale that is too large. 2) Merging the viewports isn't ideal, as for example viewports with boundaries [0,1] and [1000, 1001] would allow a guardband scale of ~30k, while their union [0, 1001] only allows a scale of ~32. The new code just determines the guardband per viewport and takes the minimum. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Acked-by: Dave Airlie <[email protected]>
* radv: Enable VK_KHR_incremental_present.Bas Nieuwenhuizen2017-04-033-1/+15
| | | | | | | Just enabling the driver-independent implementation that Jason did. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* vulkan/wsi: Plumb present regions through the common codeJason Ekstrand2017-04-031-1/+2
| | | | | | Reviewed-by: Lionel Landwerlin <[email protected]> Reviewed-by: Daniel Stone <[email protected]> Acked-by: Dave Airlie <[email protected]>
* radv: overhaul fragment shader sample positions.Dave Airlie2017-04-043-36/+67
| | | | | | | | | | | | | | | | | | The current code was broken, and I decided to redesign it instead. This puts the sample positions for all samples into the queue constant descriptor buffer after all the spill/ring descriptors. It then uses a single offset register to point how far into the samples the samples for num_samples are. This saves one user sgpr and means we only generate the sample position data in the rare single case where we need it currently. This doesn't fix the failing CTS tests without the followup fix. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: fix order of the guardband register emission.Dave Airlie2017-04-021-2/+2
| | | | | | | | | y is vert, x is horiz. Noticed in visual inspection compared to radeonsi. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: enable tessellation shaders.Dave Airlie2017-04-012-9/+10
| | | | | | | | This enables tessellation shaders and sets some values for the maximums. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: add ia_multi_vgt_param tessellation support.Dave Airlie2017-04-011-2/+30
| | | | | | | This just ports the relevant radeonsi pieces. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv/cmd: emit tessellation state.Dave Airlie2017-04-011-4/+109
| | | | | | | | | This emits the tessellation shaders and state to the command stream. It contains the logic to emit the LS/HS shaders. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv/pipeline: handle tessellation shader compilationDave Airlie2017-04-011-0/+142
| | | | | | | | | | | | | | So tess shaders have some circular dependencies, TCS needs the TES primitive mode TES needs the TCS vertices out This builds the nir for each shader first to get the info, executes a tes specific nir pass, then builds the LLVM shaders. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv/pipeline: start calculating tess stage.Dave Airlie2017-04-012-9/+208
| | | | | | | | | | | This calculates the pipeline state for tessellation. It moves the gs ring calculation down to below where the tessellation shaders will be compiled, as it needs the info from those shaders. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: add tessellation support to variant code.Dave Airlie2017-04-011-6/+9
| | | | | | | This just fills out the rsrc registers for tess shaders. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: add tessellation support to shader namingDave Airlie2017-04-011-1/+3
| | | | | Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: port polaris vgt vertex reuse workaround.Dave Airlie2017-04-012-1/+18
| | | | | | | | This ports the VGT_VERTEX_REUSE register settings for Polaris GPUs from radeonsi. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: configure tessellation distribution register.Dave Airlie2017-04-011-4/+12
| | | | | | | This just takes the radeonsi values. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: add tessellation ring allocation support. (v2)Dave Airlie2017-04-013-13/+203
| | | | | | | | | | | | This patch adds support for the offchip rings for storing tessellation factors and attribute data. It includes the register setup for the TF ring v2: always do tess ring size calcs (Bas) Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: add support for some device specific tess information.Dave Airlie2017-04-012-0/+8
| | | | | Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
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