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path: root/src/amd/vulkan/radv_pipeline.c
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* radv: Enable RB+ where possible.Bas Nieuwenhuizen2018-04-111-6/+7
| | | | | | | | | | | | | | | According to Marek, not enabling it on Stoney has a significant negative performance impact. (And I guess this might impact performance on Raven as well) The register settings are pretty much copied from radeonsi. I did not put this in the pipeline as that would make the pipeline more dependent on the format which mean we would have to have more pipelines for the meta shaders. v2: Don't clear RB+ regs if not enabled as the CLEAR_STATE packet does already. Reviewed-by: Samuel Pitoiset <[email protected]>
* radv: implement out-of-order rasterization when it's safe on VI+Samuel Pitoiset2018-04-041-2/+238
| | | | | | | | | | | | | | | | Disabled by default for now, it can be enabled with RADV_PERFTEST=outoforder. No CTS regressions on Polaris, and all Vulkan games I tested look good as well. Expect small performance improvements for applications where out-of-order rasterization can be enabled by the driver. Loosely based on RadeonSI. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: change blend_enable field to use four bits per CBSamuel Pitoiset2018-04-041-3/+5
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: scan which color blend attachments are enabledSamuel Pitoiset2018-04-041-0/+2
| | | | | | | With cb_target_enabled_4bit in order to have four bits per CB. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: put more fields in radv_blend_stateSamuel Pitoiset2018-04-041-20/+17
| | | | | | | Some will be used for further optimizations (ie. out-of-order rast). Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: do not always disable dual quad mode when chip has RbPlusSamuel Pitoiset2018-04-041-3/+17
| | | | | | | For GFX9+ only, RadeonSI does this too. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: don't use the SPI barrier management bug workaroundSamuel Pitoiset2018-04-041-0/+5
| | | | | | | Ported from RadeonSI. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: mask out high VM address bits in registers where neededSamuel Pitoiset2018-04-041-9/+9
| | | | | | | Ported from RadeonSI. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: add support for Vega12Samuel Pitoiset2018-03-281-0/+1
| | | | | | | Based on RadeonSI. Untested. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: add support for VK_EXT_depth_range_unrestrictedSamuel Pitoiset2018-03-201-0/+22
| | | | | | | | | | | | | | | | This extension removes the restrictions on minDepth/maxDepth, minDepthBounds/maxDepthBounds and VkClearDepthStencilValue::depth. The following CTS tests now pass: dEQP-VK.glsl.builtin_var.fragdepth.line_list_d32_sfloat_large_depth dEQP-VK.glsl.builtin_var.fragdepth.point_list_d32_sfloat_large_depth dEQP-VK.glsl.builtin_var.fragdepth.triangle_list_d32_sfloat_large_depth dEQP-VK.draw.inverted_depth_ranges.nodepthclamp_depth_range_unrestricted dEQP-VK.draw.inverted_depth_ranges.depthclamp_depth_range_unrestricted Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: handle exporting view index to fragment shader. (v1.1)Dave Airlie2018-03-191-0/+4
| | | | | | | | | | | | | | | | The fragment shader was trying to read this, but nothing was exporting it from the vertex shader. This handles it like the prim id export. Fixes: dEQP-VK.multiview.secondary_cmd_buffer.* dEQP-VK.multiview.index.fragment_shader.* v1.1: updated to use 0x1 (Samuel) Fixes: e3265c10c89 (radv: Implement multiview draws.) Reviewed-by: Samuel Pitoiset <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: drop geometry stride user sgpr.Dave Airlie2018-03-161-9/+0
| | | | | | | This removes the other geometry specific user sgpr. Reviewed-by: Samuel Pitoiset <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: get rid of geometry user sgpr for num entries.Dave Airlie2018-03-161-8/+1
| | | | | | | | This drops one of the geometry specific user sgprs, we can work this out at compile time. Reviewed-by: Samuel Pitoiset <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: migrate lds size calculations to shader gen.Dave Airlie2018-03-161-25/+4
| | | | | | | | This moves the lds_size calcs into the shader so we have all the size stuff in one file. Reviewed-by: Samuel Pitoiset <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: drop scanning the tess shader in the nir code.Dave Airlie2018-03-161-4/+3
| | | | | | | | This drops the now unneeded scanning and results in favour of the ones in the info. Reviewed-by: Samuel Pitoiset <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: use num_patches output from tcs shader.Dave Airlie2018-03-161-28/+2
| | | | | | | Instead of recalculating the value, use the shader calculated value. Reviewed-by: Samuel Pitoiset <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv/tess: remove last chunk of tess sgprsDave Airlie2018-03-161-16/+2
| | | | | | | This removes the last TES-specifc user sgpr. Reviewed-by: Samuel Pitoiset <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: pass num_patches to tes from tcsDave Airlie2018-03-161-0/+4
| | | | | | | TES needs num_patches to do some of the calculations. Reviewed-by: Samuel Pitoiset <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: drop tess offchip layout for tcs.Dave Airlie2018-03-161-9/+0
| | | | | | | This removes the last TCS specific user sgpr. Reviewed-by: Samuel Pitoiset <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: drop tcs_out_offsetsDave Airlie2018-03-161-8/+2
| | | | | | | Move all calculations to shader generation. Reviewed-by: Samuel Pitoiset <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: drop tcs_out_layoutDave Airlie2018-03-161-6/+2
| | | | | | | Move all calculations to shader generation. Reviewed-by: Samuel Pitoiset <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv/tess: drop tcs_in_layout setting completely.Dave Airlie2018-03-161-6/+6
| | | | | | | Inline all calcs at shader creation. Reviewed-by: Samuel Pitoiset <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: drop ls_out_layout const.Dave Airlie2018-03-161-10/+0
| | | | | | | We can precalculate input_vertex_size at compile time. Reviewed-by: Samuel Pitoiset <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* ac/nir: move ac_nir_compiler_options and friends to radv folderSamuel Pitoiset2018-03-131-3/+3
| | | | | | | Also replace ac_ by radv_. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* ac/nir: move ac_shader_variant_info and friends to radv folderSamuel Pitoiset2018-03-131-11/+11
| | | | | | | Also replace ac_ by radv_. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* ac/radv: move lower_indirect_derefs() to ac_nir_to_llvm.cTimothy Arceri2018-03-051-4/+4
| | | | | | | Until llvm handles indirects better we will need to use these workarounds in the radeonsi backend also. Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* ac/shader: move scanning some info about input PS declarationsSamuel Pitoiset2018-02-281-6/+8
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: don't send num_tcs_input_cp to sgprs.Dave Airlie2018-02-211-4/+1
| | | | | | | We never use it in the shaders. Reviewed-by: Samuel Pitoiset <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv/tess: don't need to look in constant for vertices_per_patchDave Airlie2018-02-211-1/+1
| | | | | | | This just avoids passing this value via user sgprs. Reviewed-by: Samuel Pitoiset <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: compact varyings after removing unused onesSamuel Pitoiset2018-02-191-6/+3
| | | | | | | | | | | | | | | | | | | | | | | | It makes no sense to compact before, and the description of nir_compact_varyings() confirms that. Polaris10: Totals from affected shaders: SGPRS: 108528 -> 108128 (-0.37 %) VGPRS: 74548 -> 74500 (-0.06 %) Spilled SGPRs: 844 -> 814 (-3.55 %) Code Size: 3007328 -> 2992932 (-0.48 %) bytes Max Waves: 16019 -> 16009 (-0.06 %) Vega10: Totals from affected shaders: SGPRS: 106088 -> 106232 (0.14 %) VGPRS: 74652 -> 74700 (0.06 %) Spilled SGPRs: 692 -> 658 (-4.91 %) Code Size: 2967708 -> 2953028 (-0.49 %) bytes Max Waves: 18178 -> 18162 (-0.09 %) Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* radv: Always lower indirect derefs after nir_lower_global_vars_to_local.Bas Nieuwenhuizen2018-02-151-2/+9
| | | | | | | | Otherwise new local variables can cause hangs on vega. CC: <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105098 Reviewed-by: Timothy Arceri <[email protected]>
* ac/shader: scan info about output PS declarationsSamuel Pitoiset2018-02-081-9/+9
| | | | | | | | NIR->LLVM should only be a translation pass, and all scan stuff should be done before. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: do not dump meta shader statsSamuel Pitoiset2018-01-311-21/+9
| | | | | | | That's quite useless and that pollutes the output. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: Merge raster state with PM4 generation.Bas Nieuwenhuizen2018-01-301-65/+50
| | | | | Reviewed-by: Dave Airlie <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* radv: Move gs state out of pipeline.Bas Nieuwenhuizen2018-01-301-35/+43
| | | | | Reviewed-by: Dave Airlie <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* radv: Split out cliprect rule generation.Bas Nieuwenhuizen2018-01-301-24/+33
| | | | | Reviewed-by: Dave Airlie <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* radv: Merge VGT_GS_MODE computation with PM4 generation.Bas Nieuwenhuizen2018-01-301-26/+25
| | | | | Reviewed-by: Dave Airlie <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* radv: Split out processing the vertex input state.Bas Nieuwenhuizen2018-01-301-35/+43
| | | | | Reviewed-by: Dave Airlie <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* radv: Move tessellation state out of pipeline.Bas Nieuwenhuizen2018-01-301-37/+58
| | | | | Reviewed-by: Dave Airlie <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* radv: Move blend state out of pipeline.Bas Nieuwenhuizen2018-01-301-55/+72
| | | | | Reviewed-by: Dave Airlie <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* radv: Split out generating VGT_SHADER_STAGES_EN.Bas Nieuwenhuizen2018-01-301-23/+27
| | | | | Reviewed-by: Dave Airlie <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* radv: Split out the ia_multi_vgt_param precomputation.Bas Nieuwenhuizen2018-01-301-79/+90
| | | | | | | | | Also moved everything in a struct and then return the struct from the helper function, so it is clear in the caller what part of the pipeline gets modified. Reviewed-by: Dave Airlie <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* radv: Split out db_shader_control computation.Bas Nieuwenhuizen2018-01-301-21/+22
| | | | | Reviewed-by: Dave Airlie <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* radv: Compute shader_z_format when emitting it.Bas Nieuwenhuizen2018-01-301-7/+3
| | | | | Reviewed-by: Dave Airlie <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* radv: Merge depth stencil state with PM4 generation.Bas Nieuwenhuizen2018-01-301-65/+58
| | | | | Reviewed-by: Dave Airlie <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* radv: Merge ps_input_cntl computation with PM4 generation.Bas Nieuwenhuizen2018-01-301-81/+79
| | | | | Reviewed-by: Dave Airlie <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* radv: Merge vtx_reuse_depth computation with PM4 generation.Bas Nieuwenhuizen2018-01-301-7/+6
| | | | | Reviewed-by: Dave Airlie <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* radv: Merge vs state computation with PM4 generation.Bas Nieuwenhuizen2018-01-301-50/+34
| | | | | Reviewed-by: Dave Airlie <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* radv: Merge binning state generation with pm4 emission.Bas Nieuwenhuizen2018-01-301-29/+19
| | | | | | | We don't need the pipeline state struct anymore. Reviewed-by: Dave Airlie <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* radv: Constify some pipeline helpers.Bas Nieuwenhuizen2018-01-301-4/+4
| | | | | Reviewed-by: Dave Airlie <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
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