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* ac: clean up ac_build_indexed_load function interfacesMarek Olšák2017-10-173-36/+42
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* ac: add radeon_info::has_sync_filecros-mesa-17.2.3-vanillachadv/cros-mesa-17.2.3-vanillaMarek Olšák2017-10-122-0/+2
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* ac/surface: add ac_surface::is_displayableMarek Olšák2017-10-122-0/+13
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* amd: move r600d_common.h into r600gMarek Olšák2017-10-091-135/+0
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: shrink r600d_common.h and stop using itMarek Olšák2017-10-092-165/+17
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* ac: properly document a buffer.store LLVM workaroundMarek Olšák2017-10-062-6/+9
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* ac: silence a warningMarek Olšák2017-10-041-1/+3
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* radv: emit fmuladd instead of fma to llvm.Dave Airlie2017-10-041-1/+1
| | | | | | | | | | | | | | | | | | | | For Vulkan SPIR-V the spec states fma() Inherited from OpFMul followed by OpFAdd. Matt says the backend will do the right thing depending on the hardware being compiled for, if you use the fmuladd intrinsic. Using the Mad Max pts test, on high settings at 4K: CHP: 55->60 HGDD: 46->50 LM: 55->60 No change on Stronghold. Thanks to Feral for spending the time to track this down. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Cc: "17.2" <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* amd/common: move ac_build_phi from radeonsiNicolai Hähnle2017-10-022-0/+19
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: clamp depth comparison value only for fixed point formatsNicolai Hähnle2017-09-291-0/+2
| | | | | | | | | | | | | | | | | | | The hardware usually does this automatically. However, we upgrade depth to Z32_FLOAT to enable TC-compatible HTILE, which means the hardware no longer clamps the comparison value for us. The only way to tell in the shader whether a clamp is required seems to be to communicate an additional bit in the descriptor table. While VI has some unused bits in the resource descriptor, those bits have unfortunately all been used in gfx9. So we use an unused bit in the sampler state instead. Fixes dEQP-GLES3.functional.texture.shadow.2d.linear.equal_depth_component32f and many other tests in dEQP-GLES3.functional.texture.shadow.* Fixes: d4d9ec55c589 ("radeonsi: implement TC-compatible HTILE") Reviewed-by: Marek Olšák <[email protected]> Tested-by: Dieter Nützel <[email protected]>
* amd/common: save an instruction in the build_cube_select sequenceNicolai Hähnle2017-09-291-5/+6
| | | | | | | Avoid a v_cndmask: the absolute value is free due to input modifiers. Reviewed-by: Marek Olšák <[email protected]> Tested-by: Dieter Nützel <[email protected]>
* amd/common: fix build_cube_selectNicolai Hähnle2017-09-291-3/+3
| | | | | | | | | | | | Fix the custom cube coord selection sequence to be identical to the hardware v_cubesc/tc and OpenGL spec. Affects texture sampling with user-provided derivatives. Fixes dEQP-GLES3.functional.shaders.texture_functions.texturegrad.* Cc: [email protected] Reviewed-by: Marek Olšák <[email protected]> Tested-by: Dieter Nützel <[email protected]>
* amd/common: remove ac_shader_abi::chip_classNicolai Hähnle2017-09-292-13/+10
| | | | | | | Redundant with the recently added ac_llvm_context::chip_class. Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* meson: build "radv" vulkan driver for radeon hardwareDylan Baker2017-09-271-0/+63
| | | | | | | | | | | | | | | | This builds, installs, and has been tested on a r290x (Hawaii) with the Vulkan CTS. It dies horribly in a fire at the same point for the meson build as the autotools build. v2: - enable radv by default - add shader cache support and enforce that it's built for radv v3: - Fix typo in meson_options (Nicholas) - strip trailing 'svn' from llvm version before setting the version preprocessor flag (Bas) - Check for LLVM module requirements Signed-off-by: Dylan Baker <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* ac/surface: handle error when choosing preferred swizzle modeNicolai Hähnle2017-09-211-2/+4
| | | | | | | CID: 1418140 Fixes: c4ac522511d2 ("ac/surface: handle S8 on gfx9") Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* ac/surface: handle S8 on gfx9Dave Airlie2017-09-201-2/+7
| | | | | | | | | | | | If we don't have a depth piece, we don't get a correct swizzle mode and we hit an assert in addrlib. In case of no depth get the preferrred swizzle mode for stencil alone. Reviewed-by: Marek Olšák <[email protected]> Cc: "17.2" <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* amd/common: add workaround for cube map array layer clampingNicolai Hähnle2017-09-181-2/+29
| | | | | | | Fixes dEQP-GLES31.functional.texture.filtering.cube_array.* Cc: [email protected] Reviewed-by: Marek Olšák <[email protected]>
* amd/common: remove has_ds_bpermute argument from ac_build_ddxyNicolai Hähnle2017-09-183-7/+2
| | | | Reviewed-by: Marek Olšák <[email protected]>
* amd/common: add chip_class to ac_llvm_contextNicolai Hähnle2017-09-183-4/+12
| | | | Reviewed-by: Marek Olšák <[email protected]>
* amd/common: round cube array slice in ac_prepare_cube_coordsNicolai Hähnle2017-09-183-5/+8
| | | | | | | | | | | | The NIR-to-LLVM pass already does this; now the same fix covers radeonsi as well. Fixes various tests of dEQP-GLES31.functional.texture.filtering.cube_array.combinations.* Cc: [email protected] Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: Check for GFX9 for 1D arrays in image_size intrinsic.Bas Nieuwenhuizen2017-09-151-1/+2
| | | | | | | | | | | | | | | | | | | | | Only on GFX9 we implement them as 2D images. This fixes: dEQP-VK.image.image_size.1d_array.readonly_12x34 dEQP-VK.image.image_size.1d_array.readonly_1x1 dEQP-VK.image.image_size.1d_array.readonly_32x32 dEQP-VK.image.image_size.1d_array.readonly_7x1 dEQP-VK.image.image_size.1d_array.readonly_writeonly_12x34 dEQP-VK.image.image_size.1d_array.readonly_writeonly_1x1 dEQP-VK.image.image_size.1d_array.readonly_writeonly_32x32 dEQP-VK.image.image_size.1d_array.readonly_writeonly_7x1 dEQP-VK.image.image_size.1d_array.writeonly_12x34 dEQP-VK.image.image_size.1d_array.writeonly_1x1 dEQP-VK.image.image_size.1d_array.writeonly_32x32 dEQP-VK.image.image_size.1d_array.writeonly_7x1 Fixes: 1bcb953e166 "radv: handle GFX9 1D textures" Reviewed-by: Dave Airlie <[email protected]>
* radeonsi: move si_get_wave_info() to AMD common codeSamuel Pitoiset2017-09-142-0/+94
| | | | | | | | This will allow us to use it from radv. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* ac/surface: match Z and stencil tile configNicolai Hähnle2017-09-131-7/+42
| | | | | | | Fixes various piglit tests on Stoney, see the comment. Cc: [email protected] Reviewed-by: Marek Olšák <[email protected]>
* ac/surface: sanity-check that we got a TC-compatible HTILE if requestedNicolai Hähnle2017-09-131-0/+6
| | | | Reviewed-by: Marek Olšák <[email protected]>
* amd/common: get ME/PFP/CE firmware feature versions as wellNicolai Hähnle2017-09-132-4/+9
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radv/ac: bump params array for image atomic comp swapDave Airlie2017-09-131-1/+1
| | | | | | | | | | | | For the comp_swap case this was overflowing and crashing sometimes. Fixes: dEQP-VK.image.atomic_operations.compare_exchange.* Cc: "17.2" <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: handle GFX9 1D texturesDave Airlie2017-09-131-11/+69
| | | | | | | | | | | | As GFX9 can't handle 1D depth textures, radeonsi and apparantly pro just update all 1D textures to 2D, and work around it. This ports the workarounds from radeonsi. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Cc: "17.2" <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* ac: remove bitcast_to_float()Connor Abbott2017-09-081-16/+2
| | | | | | ac_to_float() does a superset of what it does. Signed-off-by: Dave Airlie <[email protected]>
* ac: move ac_to_integer() and ac_to_float() to ac_llvm_build.cConnor Abbott2017-09-083-162/+172
| | | | | | We'll need to use ac_to_integer() for other stuff in ac_llvm_build.c. Reviewed-by: Dave Airlie <[email protected]>
* ac: fix ac_get_type_size() for doublesConnor Abbott2017-09-081-0/+1
| | | | Reviewed-by: Dave Airlie <[email protected]>
* radv/ac: use ac_get_type_size.Dave Airlie2017-09-081-23/+3
| | | | | | Just moved to newly shared code. Signed-off-by: Dave Airlie <[email protected]>
* radeonsi: move the guts of ARB_shader_group_vote emission to acConnor Abbott2017-09-082-0/+36
| | | | | | Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radeonsi: move si_emit_ballot() to acConnor Abbott2017-09-082-0/+29
| | | | | | Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radeonsi: move emit_optimization_barrier() to acConnor Abbott2017-09-082-0/+45
| | | | | | Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radeonsi: move llvm_get_type_size() to acConnor Abbott2017-09-082-0/+26
| | | | | | Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* ac/surface: add radeon_surf::has_stencil for convenienceMarek Olšák2017-09-072-0/+3
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* ac/surface: reduce gfx9_surface_layout size.Dave Airlie2017-09-071-2/+3
| | | | | | 152->144. Signed-off-by: Dave Airlie <[email protected]>
* ac/debug: take ASIC generation into account when printing registersNicolai Hähnle2017-09-062-107/+177
| | | | | | | | | | | There were some overlapping changes in gfx9 especially in the CB/DB blocks which made register dumps rather misleading. The split is along the lines of the header files, so we'll print VI-only fields on SI and CI, for example, but we won't print GFX9 fields on SI/CI/VI, and we won't print SI/CI/VI fields on GFX9. Acked-by: Marek Olšák <[email protected]>
* amd/common: pass chip_class to ac_dump_regNicolai Hähnle2017-09-062-45/+45
| | | | Acked-by: Marek Olšák <[email protected]>
* ac/sid_tables: add FieldTable objectNicolai Hähnle2017-09-061-30/+85
| | | | | | | | Automatically re-use table entries like StringTable and IntTable do. This allows us to get rid of the "fields_owner" logic, and simplifies the next change. Acked-by: Marek Olšák <[email protected]>
* ac/sid_tables: remove unused variable varname_valuesNicolai Hähnle2017-09-061-1/+0
| | | | Acked-by: Marek Olšák <[email protected]>
* radv/gfx9: fix buffer size on gfx9.Dave Airlie2017-09-061-1/+1
| | | | | | | | | | The VI sizing only applies to VI. This fixes: dEQP-VK.image.image_size.buffer.* Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* ac: reorg ac_shader_binary struct to take less space.Dave Airlie2017-09-041-8/+9
| | | | | | | | This reduces the size from 96 to 80 bytes but putting all the 32-bit sizes at the start. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radeonsi: move si_vm_fault_occured() to AMD common codeSamuel Pitoiset2017-09-012-0/+113
| | | | | | | | For radv, in order to report VM faults when detected. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* ac/debug: Support multiple trace ids for nested IBs.Bas Nieuwenhuizen2017-08-292-22/+40
| | | | | Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* ac/nir: remove misleading conditionGrazvydas Ignotas2017-08-291-1/+1
| | | | | | | | | location is never set to INTERP_SAMPLE, and Nicolai comments: "... that part is misleading. location refers to the base location, not the final location of the sample, and it can never be INTERP_SAMPLE." Suggested-by: Nicolai Hähnle <[email protected]> Signed-off-by: Grazvydas Ignotas <[email protected]>
* ac/nir: silence maybe-uninitialized warningsGrazvydas Ignotas2017-08-291-6/+9
| | | | | | | | | | These are likely false positives, but are also annoying because they show up on every "make install", which causes ac_nir_to_llvm to be rebuilt here. Initializing those variables to NULL should be harmless even when unnecessary. Signed-off-by: Grazvydas Ignotas <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* amd: add .editorconfigGrazvydas Ignotas2017-08-291-0/+3
| | | | | | | | | amd/common/ and amd/vulkan/ are using tabs for indent, which doesn't match the settings in root .editorconfig, so let's override. Signed-off-by: Grazvydas Ignotas <[email protected]> Acked-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: set EVENT_WRITE_EOP.INT_SEL = wait for write confirmationMarek Olšák2017-08-281-0/+3
| | | | | | | Ported from Vulkan. Not sure what this is good for.. maybe write confirmation from L2 flushes? Reviewed-by: Nicolai Hähnle <[email protected]>
* Revert "radeonsi: get the raster config from AMDGPU on SI"Marek Olšák2017-08-272-5/+0
| | | | | | | | | | | | This reverts commit fc99cb3c9edee3af773700cf7ebdc60dc02fcaba. "The performance went down from 64.7 to 51.4 fps in Valley and from 30.8 to 25.1 fps in Heaven on Radeon HD 7970. Other games seem to have also a 10-25% performance decrease." Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102429 It looks like we can't use the raster config values from the kernel.
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