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* ac/nir: move all RADV related code to radv_nir_to_llvm.cSamuel Pitoiset2018-03-132-3420/+0
| | | | | | | | Now the "ac/nir" prefix will really be the shared code between RadeonSI and RADV, that might avoid confusions in the future. Signed-off-by: Samuel Pitoiset <[email protected]> Acked-by: Bas Nieuwenhuizen <[email protected]>
* ac/nir: make emit_barrier() non-staticSamuel Pitoiset2018-03-132-4/+6
| | | | | | | Required in order to move all RADV specific code outside of ac/nir. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* ac/nir: move radeon_llvm_reg_index_soa() to ac_nir_to_llvm.hSamuel Pitoiset2018-03-132-5/+5
| | | | | | | Required in order to move all RADV specific code outside of ac/nir. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* ac/nir: make handle_shader_output_decl() non-staticSamuel Pitoiset2018-03-132-10/+18
| | | | | | | Required in order to move all RADV specific code outside of ac/nir. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* ac/nir: change prototype of handle_shader_output_decl()Samuel Pitoiset2018-03-131-14/+14
| | | | | | | This allows to remove the ac_nir_context dependency. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* ac/nir: move unpack_param() to ac_llvm_build.cSamuel Pitoiset2018-03-133-33/+35
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* ac/nir: move trim_vector to ac_llvm_build.cSamuel Pitoiset2018-03-133-24/+27
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* ac/nir: move cast_ptr() to ac_llvm_build.cSamuel Pitoiset2018-03-133-10/+13
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* ac/nir: move ac_build_alloca() to ac_llvm_build.cSamuel Pitoiset2018-03-133-39/+41
| | | | | | | As well as si_build_alloca_undef() and drop the si prefix. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* ac/gpu_info: print ib_start_alignment, add assertionMarek Olšák2018-03-091-0/+2
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* ac/nir: set number of channels for packed mrt exportsSamuel Pitoiset2018-03-091-0/+5
| | | | | | | | Bit 0 enables VSRC0 (R in low bits, G high) and bit 2 enables VSRC1 (B in low bits, A high). Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* winsys/amdgpu: query GDS infoMarek Olšák2018-03-082-0/+13
| | | | Reviewed-by: Alex Deucher <[email protected]>
* radeonsi: align command buffer starting address to fix some Raven hangsMarek Olšák2018-03-082-1/+21
| | | | | | Cc: 17.3 18.0 <[email protected]> Reviewed-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* ac/nir: do not emit unnecessary null exports in fragment shadersSamuel Pitoiset2018-03-081-13/+16
| | | | | | | | | | | | | | | | | | | | Null exports should only be needed when no other exports are emitted. This removes a bunch of 'exp null off, off, off, off done vm'. Affected games are Dota 2 and Wolfenstein 2, not sure if that really helps, but code size is decreasing there. Polaris10: Totals from affected shaders: SGPRS: 8216 -> 8216 (0.00 %) VGPRS: 7072 -> 7072 (0.00 %) Spilled SGPRs: 0 -> 0 (0.00 %) Spilled VGPRs: 0 -> 0 (0.00 %) Code Size: 454968 -> 453896 (-0.24 %) bytes Max Waves: 772 -> 772 (0.00 %) Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* ac/radeonsi: add emit_kill to the abiTimothy Arceri2018-03-082-1/+10
| | | | | | | | This should fix a regression with Rocket League grass rendering on the NIR backend. Reviewed-by: Marek Olšák <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104717
* ac: make use of if/loop build helpersTimothy Arceri2018-03-081-42/+18
| | | | | | | | | | | | These helpers insert the basic block in the same order as they appear in NIR making it easier to follow LLVM IR dumps. The helpers also insert more useful labels onto the blocks. TGSI use the line number of the corresponding opcode in the TGSI dump as the label id, here we use the corresponding block index from NIR. Reviewed-by: Marek Olšák <[email protected]>
* ac: add if/loop build helpersTimothy Arceri2018-03-083-0/+211
| | | | | | These have been ported over from radeonsi. Reviewed-by: Marek Olšák <[email protected]>
* ac: implement AMD_gcn_shader extended instructionsDaniel Schürmann2018-03-071-0/+28
| | | | | | Co-authored-by: Dave Airlie <[email protected]> Signed-off-by: Daniel Schürmann <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: Add minimal subgroup support.Bas Nieuwenhuizen2018-03-072-0/+51
| | | | | | | Deliberately not implementing workgroup scopes as that is not needed for core vulkan. Reviewed-by: Dave Airlie <[email protected]>
* ac/nir: Add vote_ieq/vote_feq lowering pass.Bas Nieuwenhuizen2018-03-074-5/+98
| | | | | | | | | | | | The old vote_eq implementation supported only booleans, but now we have to support arbitrary values, so use the read_first_invocation intrinsic + ballot. I took this as an opportunity to figure out how easy it was to do this in nir instead of in the nir_to_llvm pass, and it actually turned out pretty okay IMO. Only creating the pass is some extra code. Reviewed-by: Dave Airlie <[email protected]>
* nir: Generalize nir_intrinsic_vote_eqJason Ekstrand2018-03-071-1/+1
| | | | | | | | | | | | | The SPIR-V extension wants us to be able to do an AllEqual on any vector or scalar type. This has two implications: 1) We need to be able to handle vectors so we switch the vote_eq intrinsics to be vectorized intrinsics. 2) We need to handle floats which have different behavior with respect to +-0, NaN, etc. than the integer variant so we need two variants. Reviewed-by: Lionel Landwerlin <[email protected]>
* radeonsi: fix passing address32_hi to LLVM for high valuesMarek Olšák2018-03-072-3/+3
| | | | The old function treats high values as negative, which LLVM interprets as 0.
* ac/nir: don't put lod into args if it's zero.Dave Airlie2018-03-071-2/+1
| | | | | | | | | | | If it's zero but put it in args we still end up consuming a register for it. This fixes some spilling in the NIR paths in Dirt Rally that isn't seen with TGSI. Reviewed-by: Timothy Arceri <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* ac/nir: count the scratch private memory sizeSamuel Pitoiset2018-03-062-2/+9
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* ac: add ac_count_scratch_private_memory()Samuel Pitoiset2018-03-062-0/+34
| | | | | | | Imported from RadeonSI. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* ac/nir: only enable used channels when exporting parametersSamuel Pitoiset2018-03-061-4/+20
| | | | | | | | | | This allows us to generate, for example, "exp param0 v0, off, off, off" if only the first channel is needed. Not sure if this improves performance but it's worth trying. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* ac: update enabled channels mask when optimizing PARAM exportsSamuel Pitoiset2018-03-061-2/+16
| | | | | | | | | When the mask is not 0xf we need to update the number of enabled channels, otherwise the hardware won't emit the components that are combined. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* ac/nir: pass the number of enabled channels to si_llvm_init_export_args()Samuel Pitoiset2018-03-061-8/+13
| | | | | | | | Currently, it's always 0xf but an upcoming patch will reduce the number of channels for parameters export. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* ac/shader: scan output usage mask for VS and TESSamuel Pitoiset2018-03-062-0/+22
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* ac: pass the unmodified number of components to load gs inputsTimothy Arceri2018-03-061-2/+2
| | | | | | | | | | | Currently both users of this would overflow an array when the input was a dual slot double as they expected the number of components to be a max of 4. Since we pass the type we can just let the functions handle doubles in a way they choose. Reviewed-by: Dave Airlie <[email protected]>
* ac: add ac_build_fsign()Samuel Pitoiset2018-03-053-25/+28
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* ac: add ac_build_isign()Samuel Pitoiset2018-03-053-24/+28
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* ac: add ac_build_fract()Samuel Pitoiset2018-03-053-26/+34
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* ac/radv: move lower_indirect_derefs() to ac_nir_to_llvm.cTimothy Arceri2018-03-052-0/+39
| | | | | | | Until llvm handles indirects better we will need to use these workarounds in the radeonsi backend also. Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* ac: fix nir_intrinsic_shared_atomic_comp_swap handlingTimothy Arceri2018-03-021-1/+1
| | | | | | | | | | Following on from 49879f377870 this makes sure we use the correct src index. Fixes cts test: KHR-GL46.compute_shader.atomic-case3 Reviewed-by: Dave Airlie <[email protected]>
* ac/nir: fix shared atomic operations.Dave Airlie2018-03-011-5/+5
| | | | | | | | | | | The nir->llvm conversion was using the wrong srcs. Fixes: tests/spec/arb_compute_shader/execution/shared-atomics.shader_test Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Timothy Arceri <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* ac/nir: don't apply slice rounding on txf_msDave Airlie2018-03-011-1/+1
| | | | | | | | | | | This matches the tgsi code. Fixes arb_texture_multisample texelFetch piglit tests. Reviewed-by: Timothy Arceri <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Fixes: f4e499ec7914 (radv: add initial non-conformant radv vulkan driver) Signed-off-by: Dave Airlie <[email protected]>
* ac/shader: move scanning some info about input PS declarationsSamuel Pitoiset2018-02-284-9/+18
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* ac/radv: move load base vertex abi setup to vertex shader.Dave Airlie2018-02-281-1/+1
| | | | | | | | | This was segfaulting: dEQP-VK.memory.pipeline_barrier.host_write_index_buffer.1024 Fixes: 8de6f797070 (ac/radeonsi: add load_base_vertex() to the abi) Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* ac/shader: fix vertex input with components.Dave Airlie2018-02-281-1/+1
| | | | | | | | | | This fixes: dEQP-VK.glsl.440.linkage.varying.component.* Fixes: 1c57a6da5e3 (ac/shader: scan vertex inputs usage mask) Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* ac: implement nir_op_ldexpTimothy Arceri2018-02-281-0/+7
| | | | Reviewed-by: Marek Olšák <[email protected]>
* ac: fix nir_op_fdd{x,y} handlingTimothy Arceri2018-02-281-2/+2
| | | | | | | | | | | | | | | radeonsi, i965 and anv all treat fdd{x,y} opcodes the same as fdd{x,y}_coarse by default. The SPIR-V spec lets the implementation decide how it should be handled and radv was previously going for the higher quality option. Here we change the shared amd code to match how nir_op_fdd{x,y} is expected to be handled by the other NIR drivers. Fixes piglit test: ./bin/arb_shader_texture_lod-texgrad -auto Reviewed-by: Dave Airlie <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* ac/radeonsi: add load_base_vertex() to the abiTimothy Arceri2018-02-282-1/+9
| | | | | | | | | | Fixes the following piglit tests: ./bin/arb_shader_draw_parameters-basevertex basevertex -auto -fbo ./bin/arb_shader_draw_parameters-basevertex basevertex-baseinstance -auto -fbo Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* ac: add support for handling nir_intrinsic_load_vertex_idTimothy Arceri2018-02-281-0/+4
| | | | | | | This will be used by radeonsi. Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* ac: fix f2b and i2b for doublesTimothy Arceri2018-02-281-2/+4
| | | | | | | | Without this llvm was asserting in debug builds. V2: use LLVMConstNull() Reviewed-by: Samuel Pitoiset <[email protected]>
* ac/nir: clean up a hack about rounding 2nd coord componentSamuel Pitoiset2018-02-271-3/+5
| | | | | | | | It's basically just the opposite, and it only makes sense to round the layer for 2D texture arrays. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* ac/nir: use ordered float comparisons except for not equalSamuel Pitoiset2018-02-261-3/+3
| | | | | | | | | | | | | | | | | | Original patch from Timothy Arceri, I have just fixed the not equal case locally. This fixes one important rendering issue in Wolfenstein 2 (the cutscene transition issue). RadeonSI uses the same ordered comparisons, so I guess that what we should do as well. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104302 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104905 Cc: <[email protected]> Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Connor Abbott <[email protected]>
* ac: make use of ac_get_llvm_num_components() helperTimothy Arceri2018-02-261-5/+1
| | | | Reviewed-by: Samuel Pitoiset <[email protected]>
* ac/nir: remove emission of nir_op_fpowSamuel Pitoiset2018-02-221-4/+0
| | | | | | | fpow is now lowered at NIR level. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* ac/nir: set GLC=1 for load/store of coherent/volatile imagesSamuel Pitoiset2018-02-221-3/+4
| | | | | | | | | | This disables persistence accross wavefronts. F1 2017 and Wolfenstein 2 appear to use some coherent images but this patch doesn't seem to change anything. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
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