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* radeonsi: shrink r600d_common.h and stop using itMarek Olšák2017-10-091-0/+17
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: clamp depth comparison value only for fixed point formatsNicolai Hähnle2017-09-291-0/+2
| | | | | | | | | | | | | | | | | | | The hardware usually does this automatically. However, we upgrade depth to Z32_FLOAT to enable TC-compatible HTILE, which means the hardware no longer clamps the comparison value for us. The only way to tell in the shader whether a clamp is required seems to be to communicate an additional bit in the descriptor table. While VI has some unused bits in the resource descriptor, those bits have unfortunately all been used in gfx9. So we use an unused bit in the sampler state instead. Fixes dEQP-GLES3.functional.texture.shadow.2d.linear.equal_depth_component32f and many other tests in dEQP-GLES3.functional.texture.shadow.* Fixes: d4d9ec55c589 ("radeonsi: implement TC-compatible HTILE") Reviewed-by: Marek Olšák <[email protected]> Tested-by: Dieter Nützel <[email protected]>
* ac/sid.h: don't use parentheses in PKT3_RELEASE_MEM definitionMarek Olšák2017-06-191-1/+1
| | | | | | | The parses skips the line if it contains parentheses. Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* ac: parse EVENT_WRITE_EOP, RELEASE_MEM, WAIT_REG_MEM, NOWHEREMarek Olšák2017-06-191-0/+1
| | | | | Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radv: flush f32->f16 conversion denormals to zero. (v2)Dave Airlie2017-05-031-0/+13
| | | | | | | | | | | | | | | SPIR-V defines the f32->f16 operation as flushing denormals to 0, this compares the class using amd class opcode. Thanks to Matt Arsenault for figuring it out. This fix is VI+ only, add a TODO for SI/CIK. This fixes: dEQP-VK.spirv_assembly.instruction.compute.opquantize.flush_to_zero Acked-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: Add top of pipe timestamp queries.Bas Nieuwenhuizen2017-05-021-0/+1
| | | | | | | Does not fix brokenness with the ready bit. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radeonsi/gfx9: CP DMA changesMarek Olšák2017-03-301-0/+1
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* amd: GFX9 packet changesMarek Olšák2017-03-301-9/+21
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* amd: add texture format definitions for GFX9Marek Olšák2017-03-301-12/+12
| | | | | | | | the DATA_FORMAT and NUM_FORMAT fields are the same, but some of the enums differ, thus add GFX6 and GFX9 suffixes, so that the IB parser can show enums for both. Reviewed-by: Nicolai Hähnle <[email protected]>
* amd: resolve remaining definition conflicts with gfx9d.hMarek Olšák2017-03-301-30/+30
| | | | | | | | Add _GFX6 and _GFX9 suffixes to conflicting definitions. sid.h and gfx9d.h can now be included in the same file. Reviewed-by: Nicolai Hähnle <[email protected]>
* amd: normalize register definition formattingMarek Olšák2017-03-301-60/+78
| | | | | | | This resolves trivial conflicts with gfx9d.h caused by different formatting. Some fields are also renamed. Reviewed-by: Nicolai Hähnle <[email protected]>
* amd/common: document PREDICATION OP 3 as 64-bit bool.Dave Airlie2017-03-071-0/+1
| | | | | | | This just documents some info for possible future use. Reviewed-by: Marek Olšák <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* ac/debug: Dump indirect buffers.Bas Nieuwenhuizen2017-01-091-0/+2
| | | | | | | | | | | | | | This is for handling chained command buffers and secondary command buffers. It doesn't handle the trace id for secondary command buffers yet, but I don't think that is possible in general with just writes, as we could call a secondary command buffer multiple times. I think this is good enough for now, as the most useful case is the chaining when we grow an IB. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radeonsi: do all math in bytes in SI DMA codeMarek Olšák2017-01-051-2/+4
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radv: Use RELEASE_MEM packet for MEC timestamp query.Bas Nieuwenhuizen2016-12-181-0/+1
| | | | | Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radeonsi: document a CP DMA bug that doesn't need a workaround yetMarek Olšák2016-12-011-1/+5
| | | | | | This one is easy to miss, because it's not documented in any internal doc. Reviewed-by: Nicolai Hähnle <[email protected]>
* amd: fix a typo in PIXEL_PIPE_STAT_RESET definitionMarek Olšák2016-11-011-1/+1
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: fix a ZPASS comment, EVENT_WRITE_EOP fixupsMarek Olšák2016-10-261-1/+1
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: move sid.h/r600d_common.h to a common place.Dave Airlie2016-09-061-0/+9057
Step one to merging radv would be to move some files around. This only adds the include path to r600/radeonsi, because later we want to avoid having to add it to the generic target paths. Acked-by: Marek Olšák <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>