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* radv/gfx10: set the pgm rsrc3/4 regs using index sh reg setDave Airlie2019-07-181-0/+1
| | | | | | | | This is ported from AMDVLK, it's probably not requires unless we want to use "real time queues", but it might be nice to just have in place. Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* amd/common: use generated register headerNicolai Hähnle2019-06-031-8903/+2
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* amd/common: unify PITCH_GFX6 and PITCH_GFX9Nicolai Hähnle2019-06-031-3/+3
| | | | | | | | | | | The definition of the fields differs, but PITCH_GFX9 is a mere extension of PITCH_GFX6 that does not conflict with any other fields. This aligns the definitions with what will be generated from the register JSON. The information about how large the fields really are is preserved in the register database.
* amd/common: rename R_3F2_CONTROL to IB_CONTROL for disambiguationNicolai Hähnle2019-06-031-1/+1
| | | | | | | This "register" name collides with R_370_CONTROL. This aligns the definitions with what will be generated from the register JSON.
* amd/common: cleanup DATA_FORMAT/NUM_FORMAT field namesNicolai Hähnle2019-06-031-6/+6
| | | | | | | | | | The field layout wasn't actually changed in gfx9, so having the suffix isn't very useful. The field *contents* were changed, but this is reflected in the V_xxx_xxx definitions and is taken into account by the ac_debug logic based on the register JSON. This aligns the definitions with what will be generated from the register JSON.
* ac: add REWIND and GDS registers to register headersMarek Olšák2019-04-231-0/+16
| | | | | Tested-by: Dieter Nützel <[email protected]> Acked-by: Nicolai Hähnle <[email protected]>
* radeonsi: correct WRITE_DATA.DST_SEL definitionsMarek Olšák2019-01-221-2/+2
| | | | Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radeonsi/gfx9: use SET_UCONFIG_REG_INDEX packets when availableNicolai Hähnle2018-12-191-0/+1
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radv: remove dependency on addrlib gfx9_enum.hNicolai Hähnle2018-11-291-0/+3
| | | | | | | v2: - use SI_CONTEXT_REG_OFFSET Reviewed-by: Dave Airlie <[email protected]>
* radv: use LOAD_CONTEXT_REG when loading fast clear valuesSamuel Pitoiset2018-11-081-0/+1
| | | | | | | | | This avoids syncing the Micro Engine. This is only supported for VI+ currently. There is probably a way for using LOAD_CONTEXT_REG on previous chips but that could be done later. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: use WAIT_REG_MEM_GREATER_OR_EQUAL instead of a magic valueSamuel Pitoiset2018-10-311-0/+1
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: implement VK_EXT_transform_feedbackSamuel Pitoiset2018-10-291-0/+1
| | | | | | | | This implementation should work and potential bugs can be fixed during the release candidates window anyway. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radeonsi: rename si_gfx_* functions to si_cp_*Marek Olšák2018-10-161-0/+1
| | | | and write_event_eop -> release_mem
* radeonsi: make si_gfx_write_event_eop more configurableMarek Olšák2018-10-161-0/+5
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* ac: correct PKT3_COPY_DATA definitionsMarek Olšák2018-10-061-2/+9
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* radv: do not use the availability bit for timestamp queriesSamuel Pitoiset2018-09-281-0/+1
| | | | | | | | | | | It's unnecessary because we can just check if the timestamp is to different to the default value when a pool is created or resetted. Instead of waiting for the availability bit to be 1, we have to emit a not equal WAIT_REG_MEM for checking if the timestamp is ready. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* ac/radeonsi: fix CIK copy max sizeDave Airlie2018-08-311-1/+3
| | | | | | | | | | | | While adding transfer queues to radv, I started writing some tests, the first test I wrote fell over copying a buffer larger than this limit. Checked AMDVLK and found the correct limit. Cc: <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: add SI_QUERY_TIME_ELAPSED_SDMA for measuring SDMA performanceMarek Olšák2018-08-291-0/+4
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* radeonsi: add flag L2_STREAM for minimal cache usageMarek Olšák2018-08-291-0/+2
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* radeonsi: implement EXT_window_rectanglesMarek Olšák2018-08-141-0/+16
| | | | Reviewed-by: Samuel Pitoiset <[email protected]>
* ac: fix typo DSL_SEL -> DST_SELMarek Olšák2018-07-261-2/+2
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* radv: Translate logic ops.Bas Nieuwenhuizen2018-05-141-28/+16
| | | | | | | | | | | radeonsi could pass them through but the enum changed between Gallium and Vulkan, so we have to translate. In progress I made the register defines a bit more readable. CC: 18.0 18.1 <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100430 Reviewed-by: Samuel Pitoiset <[email protected]>
* amd/common/radv/radeonsi: use register defines for dcc block sizes.Dave Airlie2017-12-271-0/+6
| | | | | | | | These are just taken from amdvlk, we probably knew these already, but may as well port them now. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* amd/common: sid.h cleanupsNicolai Hähnle2017-11-281-13/+29
| | | | | | | Fix a bunch of labels indicating when registers were added/removed and normalize the SI-class GRBM_GFX_INDEX. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: shrink r600d_common.h and stop using itMarek Olšák2017-10-091-0/+17
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: clamp depth comparison value only for fixed point formatsNicolai Hähnle2017-09-291-0/+2
| | | | | | | | | | | | | | | | | | | The hardware usually does this automatically. However, we upgrade depth to Z32_FLOAT to enable TC-compatible HTILE, which means the hardware no longer clamps the comparison value for us. The only way to tell in the shader whether a clamp is required seems to be to communicate an additional bit in the descriptor table. While VI has some unused bits in the resource descriptor, those bits have unfortunately all been used in gfx9. So we use an unused bit in the sampler state instead. Fixes dEQP-GLES3.functional.texture.shadow.2d.linear.equal_depth_component32f and many other tests in dEQP-GLES3.functional.texture.shadow.* Fixes: d4d9ec55c589 ("radeonsi: implement TC-compatible HTILE") Reviewed-by: Marek Olšák <[email protected]> Tested-by: Dieter Nützel <[email protected]>
* ac/sid.h: don't use parentheses in PKT3_RELEASE_MEM definitionMarek Olšák2017-06-191-1/+1
| | | | | | | The parses skips the line if it contains parentheses. Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* ac: parse EVENT_WRITE_EOP, RELEASE_MEM, WAIT_REG_MEM, NOWHEREMarek Olšák2017-06-191-0/+1
| | | | | Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radv: flush f32->f16 conversion denormals to zero. (v2)Dave Airlie2017-05-031-0/+13
| | | | | | | | | | | | | | | SPIR-V defines the f32->f16 operation as flushing denormals to 0, this compares the class using amd class opcode. Thanks to Matt Arsenault for figuring it out. This fix is VI+ only, add a TODO for SI/CIK. This fixes: dEQP-VK.spirv_assembly.instruction.compute.opquantize.flush_to_zero Acked-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: Add top of pipe timestamp queries.Bas Nieuwenhuizen2017-05-021-0/+1
| | | | | | | Does not fix brokenness with the ready bit. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radeonsi/gfx9: CP DMA changesMarek Olšák2017-03-301-0/+1
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* amd: GFX9 packet changesMarek Olšák2017-03-301-9/+21
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* amd: add texture format definitions for GFX9Marek Olšák2017-03-301-12/+12
| | | | | | | | the DATA_FORMAT and NUM_FORMAT fields are the same, but some of the enums differ, thus add GFX6 and GFX9 suffixes, so that the IB parser can show enums for both. Reviewed-by: Nicolai Hähnle <[email protected]>
* amd: resolve remaining definition conflicts with gfx9d.hMarek Olšák2017-03-301-30/+30
| | | | | | | | Add _GFX6 and _GFX9 suffixes to conflicting definitions. sid.h and gfx9d.h can now be included in the same file. Reviewed-by: Nicolai Hähnle <[email protected]>
* amd: normalize register definition formattingMarek Olšák2017-03-301-60/+78
| | | | | | | This resolves trivial conflicts with gfx9d.h caused by different formatting. Some fields are also renamed. Reviewed-by: Nicolai Hähnle <[email protected]>
* amd/common: document PREDICATION OP 3 as 64-bit bool.Dave Airlie2017-03-071-0/+1
| | | | | | | This just documents some info for possible future use. Reviewed-by: Marek Olšák <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* ac/debug: Dump indirect buffers.Bas Nieuwenhuizen2017-01-091-0/+2
| | | | | | | | | | | | | | This is for handling chained command buffers and secondary command buffers. It doesn't handle the trace id for secondary command buffers yet, but I don't think that is possible in general with just writes, as we could call a secondary command buffer multiple times. I think this is good enough for now, as the most useful case is the chaining when we grow an IB. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radeonsi: do all math in bytes in SI DMA codeMarek Olšák2017-01-051-2/+4
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radv: Use RELEASE_MEM packet for MEC timestamp query.Bas Nieuwenhuizen2016-12-181-0/+1
| | | | | Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radeonsi: document a CP DMA bug that doesn't need a workaround yetMarek Olšák2016-12-011-1/+5
| | | | | | This one is easy to miss, because it's not documented in any internal doc. Reviewed-by: Nicolai Hähnle <[email protected]>
* amd: fix a typo in PIXEL_PIPE_STAT_RESET definitionMarek Olšák2016-11-011-1/+1
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: fix a ZPASS comment, EVENT_WRITE_EOP fixupsMarek Olšák2016-10-261-1/+1
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: move sid.h/r600d_common.h to a common place.Dave Airlie2016-09-061-0/+9057
Step one to merging radv would be to move some files around. This only adds the include path to r600/radeonsi, because later we want to avoid having to add it to the generic target paths. Acked-by: Marek Olšák <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
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