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* amdgpu/addrlib: support non-power2 height alignment (for linear surface)Roy Zhan2017-03-301-1/+10
* amdgpu/addrlib: Fix family setting for VI and CZ ASICsFrans Gu2017-03-301-0/+2
* amdgpu/addrlib: style cleanupNicolai Hähnle2017-03-302-28/+15
* amdgpu/addrlib: Pad pitch to multiples of 256 for DCC surface on FijiNicolai Hähnle2017-03-308-49/+131
* amdgpu/addrlib: Fix number of //Xavi Zhang2017-03-308-66/+66
* amdgpu/addrlib: Cleanup.Nicolai Hähnle2017-03-3013-73/+68
* amdgpu/addrlib: Use namespacesXavi Zhang2017-03-3016-892/+969
* amdgpu/addrlib: Adjust 99 "*" to 100 "*" alignmentKevin Zhao2017-03-3018-895/+895
* amdgpu/addrlib: Add a new tile mode ADDR_TM_UNKNOWNFrans Gu2017-03-308-14/+211
* amdgpu/addrlib: Stylish cleanup.Xavi Zhang2017-03-305-17/+16
* amdgpu/addrlib: Disable tcComaptible when depth surface is not macro tiledRoy Zhan2017-03-301-17/+20
* amdgpu/addrlib: fix pixel index calculation of thick micro tilingXavi Zhang2017-03-301-4/+4
* amdgpu/addrlib: Add a flag to skip calculate indicesXavi Zhang2017-03-303-14/+21
* amdgpu/addrlib: add equation generationNicolai Hähnle2017-03-3012-118/+1344
* amdgpu/addrlib: rename ComputeSurfaceThickness to ThicknessNicolai Hähnle2017-03-305-32/+32
* amdgpu/addrlib: add define HAVE_TSERVERXavi Zhang2017-03-302-6/+6
* amdgpu/addrlib: Add new interface to support macro mode index queryFrans Gu2017-03-304-0/+115
* amdgpu/addrlib: add explicit Log2NonPow2 functionRoy Zhan2017-03-301-8/+20
* amdgpu/addrlib: Fix invalid access to m_tileTableNicolai Hähnle2017-03-301-6/+17
* amdgpu/addrlib: add ADDR_ANALYSIS_ASSUMENicolai Hähnle2017-03-303-10/+20
* amdgpu/addrlib: add tcCompatible htile addr from coordinate support.XiaoYuan Zheng2017-03-305-13/+80
* amdgpu/addrlib: force all zero tile info for linear general.Carlos Xiong2017-03-301-1/+10
* amdgpu/addrlib: Add a member "bpp" for input of method AddrConvertTileIndex a...Nicolai Hähnle2017-03-307-32/+53
* amdgpu/addrlib: Refine the PRT tile mode selectionFrans Gu2017-03-302-51/+19
* amdgpu/addrlib: add dccRamSizeAligned output flagXavi Zhang2017-03-302-1/+7
* amdgpu/addrlib: Change comment alignmentNicolai Hähnle2017-03-301-12/+12
* amdgpu/addrlib: style changes and minor cleanupsNicolai Hähnle2017-03-3011-84/+82
* amdgpu/addrlib: AddrLib inheritance refactorNicolai Hähnle2017-03-309-560/+675
* amdgpu/addrlib: rearrange code in preparation of refactoringNicolai Hähnle2017-03-304-3528/+3593
* amdgpu/addrlib: add disableLinearOpt flagXavi Zhang2017-03-303-3/+8
* amdgpu/addrlib: Add GetMaxAlignmentsXavi Zhang2017-03-308-1/+184
* amdgpu/addrlib: Let Kaveri go general stereo right eye offset padding pathXavi Zhang2017-03-304-54/+41
* amdgpu/addrlib: Rewrite tile mode optmization codeXavi Zhang2017-03-305-24/+50
* amdgpu/addrlib: Add a flag "tcCompatible" to surface info output structure.Carlos Xiong2017-03-303-15/+50
* amdgpu/addrlib: Make comments shorterXavi Zhang2017-03-301-47/+29
* amdgpu/addrlib: add new flag nonSplitXiaoYuan Zheng2017-03-302-2/+3
* amdgpu/addrlib: allow tileSplitBytes greater than row sizeXiao-Tao Zai2017-03-301-1/+1
* amdgpu/addrlib: Change to compute TC compatible stencil infoCarlos Xiong2017-03-302-65/+59
* amdgpu/addrlib: rename SiAddrLib/CiAddrLib to match internal spellingNicolai Hähnle2017-03-304-149/+149
* radeonsi: add Polaris12 support (v3)Junwei Zhang2016-12-212-1/+3
* amd/addrlib: limit fastcall/regparm to GCC i386Emil Velikov2016-11-091-1/+5
* amd/addrlib: move addrlib from amdgpu winsys to common codeDave Airlie2016-09-0619-0/+21745
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