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path: root/src/amd/addrlib/r800
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* amd/addrlib: update to latest versionMarek Olšák2017-11-085-739/+68
* ac/addrlib: relax an assertionNicolai Hähnle2017-09-131-1/+1
* amd/addrlib: fix typo in api name.Dave Airlie2017-07-174-4/+4
* amd/addrlib: second update for Vega10 + bug fixesMarek Olšák2017-04-045-51/+93
* Partially revert "amd/addrlib: silence warnings" to fix builds with DEBUGMarek Olšák2017-03-301-3/+3
* amd/addrlib: silence warningsMarek Olšák2017-03-301-3/+3
* amd/addrlib: Adjust slie size after pitch and actual height adjustmentFrans Gu2017-03-301-26/+31
* amd/addrlib: Apply input pitch after internal pitch aligningFrans Gu2017-03-301-12/+33
* amdgpu/addrlib: Seperate 2 dcc related workarounds by different flagsNicolai Hähnle2017-03-301-2/+2
* amdgpu/addrlib: Add a new output flag to notify client that the returned tile...Nicolai Hähnle2017-03-301-0/+1
* amdgpu/addrlib: add matchStencilTileCfg and tcCompatible fixesXavi Zhang2017-03-302-14/+133
* amdgpu/addrlib: Adjust bank equation bit order based on macro tile aspect rat...Frans Gu2017-03-303-89/+277
* amdgpu/addrlib: Check prt flag for PRT_THIN1 extra padding for DCC.Xavi Zhang2017-03-306-92/+56
* amdgpu/addrlib: Add new flags minimizePadding and maxBaseAlignFrans Gu2017-03-306-106/+216
* amdgpu/addrlib: fix crash on allocation failureSabre Shao2017-03-302-2/+4
* amdgpu/addrlib: Add flag to report if a surface can have dcc ramFrans Gu2017-03-302-3/+26
* amdgpu/addrlib: Fix family setting for VI and CZ ASICsFrans Gu2017-03-301-0/+2
* amdgpu/addrlib: style cleanupNicolai Hähnle2017-03-302-28/+15
* amdgpu/addrlib: Pad pitch to multiples of 256 for DCC surface on FijiNicolai Hähnle2017-03-306-38/+120
* amdgpu/addrlib: Fix number of //Xavi Zhang2017-03-302-4/+4
* amdgpu/addrlib: Cleanup.Nicolai Hähnle2017-03-304-29/+30
* amdgpu/addrlib: Use namespacesXavi Zhang2017-03-306-377/+418
* amdgpu/addrlib: Adjust 99 "*" to 100 "*" alignmentKevin Zhao2017-03-306-298/+298
* amdgpu/addrlib: Add a new tile mode ADDR_TM_UNKNOWNFrans Gu2017-03-304-0/+176
* amdgpu/addrlib: Disable tcComaptible when depth surface is not macro tiledRoy Zhan2017-03-301-17/+20
* amdgpu/addrlib: Add a flag to skip calculate indicesXavi Zhang2017-03-302-13/+19
* amdgpu/addrlib: add equation generationNicolai Hähnle2017-03-306-73/+974
* amdgpu/addrlib: rename ComputeSurfaceThickness to ThicknessNicolai Hähnle2017-03-303-23/+23
* amdgpu/addrlib: Fix invalid access to m_tileTableNicolai Hähnle2017-03-301-6/+17
* amdgpu/addrlib: add ADDR_ANALYSIS_ASSUMENicolai Hähnle2017-03-302-2/+2
* amdgpu/addrlib: add tcCompatible htile addr from coordinate support.XiaoYuan Zheng2017-03-302-1/+50
* amdgpu/addrlib: force all zero tile info for linear general.Carlos Xiong2017-03-301-1/+10
* amdgpu/addrlib: Add a member "bpp" for input of method AddrConvertTileIndex a...Nicolai Hähnle2017-03-304-14/+30
* amdgpu/addrlib: Refine the PRT tile mode selectionFrans Gu2017-03-302-51/+19
* amdgpu/addrlib: add dccRamSizeAligned output flagXavi Zhang2017-03-301-0/+5
* amdgpu/addrlib: style changes and minor cleanupsNicolai Hähnle2017-03-306-32/+37
* amdgpu/addrlib: AddrLib inheritance refactorNicolai Hähnle2017-03-305-9/+9
* amdgpu/addrlib: Add GetMaxAlignmentsXavi Zhang2017-03-304-1/+89
* amdgpu/addrlib: Let Kaveri go general stereo right eye offset padding pathXavi Zhang2017-03-304-54/+41
* amdgpu/addrlib: Rewrite tile mode optmization codeXavi Zhang2017-03-301-0/+16
* amdgpu/addrlib: Add a flag "tcCompatible" to surface info output structure.Carlos Xiong2017-03-301-12/+39
* amdgpu/addrlib: add new flag nonSplitXiaoYuan Zheng2017-03-301-1/+1
* amdgpu/addrlib: allow tileSplitBytes greater than row sizeXiao-Tao Zai2017-03-301-1/+1
* amdgpu/addrlib: Change to compute TC compatible stencil infoCarlos Xiong2017-03-301-65/+57
* amdgpu/addrlib: rename SiAddrLib/CiAddrLib to match internal spellingNicolai Hähnle2017-03-304-149/+149
* radeonsi: add Polaris12 support (v3)Junwei Zhang2016-12-212-1/+3
* amd/addrlib: move addrlib from amdgpu winsys to common codeDave Airlie2016-09-067-0/+10142
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