summaryrefslogtreecommitdiffstats
path: root/src/amd/addrlib/r800/egbaddrlib.h
Commit message (Collapse)AuthorAgeFilesLines
* amd/addrlib: second update for Vega10 + bug fixesMarek Olšák2017-04-041-1/+1
| | | | | | | | | | | | | | | | | | | | | | | Highlights: - Display needs tiled pitch alignment to be at least 32 pixels - Implement Addr2ComputeDccAddrFromCoord(). - Macro-pixel packed formats don't support Z swizzle modes - Pad pitch and base alignment of PRT + TEX1D to 64KB. - Fix support for multimedia formats - Fix a case "PRT" entries are not selected on SI. - Fix wrong upper bits in equations for 3D resource. - We can't support 2d array slice rotation in gfx8 swizzle pattern - Set base alignment for PRT + non-xor swizzle mode resource to 64KB. - Bug workaround for Z16 4x/8x and Z32 2x/4x/8x MSAA depth texture - Add stereo support - Optimize swizzle mode selection - Report pitch and height in pixels for each mip - Adjust bpp/expandX for format ADDR_FMT_GB_GR/ADDR_FMT_BG_RG - Correct tcCompatible flag output for mipmap surface - Other fixes and cleanups Acked-by: Alex Deucher <[email protected]> Acked-by: Nicolai Hähnle <[email protected]>
* amdgpu/addrlib: Check prt flag for PRT_THIN1 extra padding for DCC.Xavi Zhang2017-03-301-6/+2
|
* amdgpu/addrlib: Add new flags minimizePadding and maxBaseAlignFrans Gu2017-03-301-2/+3
| | | | | | | | | 1) minimizePadding - Use 1D tile mode if padded size of 2D is bigger than 1D 2) maxBaseAlign - Force PRT tile mode if macro block size is bigger than requested alignment. Also, related changes to tile mode optimization for needEquation.
* amdgpu/addrlib: Pad pitch to multiples of 256 for DCC surface on FijiNicolai Hähnle2017-03-301-0/+8
| | | | | The change also modifies function CiLib::HwlPadDimensions to report adjusted pitch alignment.
* amdgpu/addrlib: Use namespacesXavi Zhang2017-03-301-5/+11
| | | | Signed-off-by: Nicolai Hähnle <[email protected]>
* amdgpu/addrlib: Adjust 99 "*" to 100 "*" alignmentKevin Zhao2017-03-301-4/+4
| | | | Signed-off-by: Nicolai Hähnle <[email protected]>
* amdgpu/addrlib: add equation generationNicolai Hähnle2017-03-301-1/+13
| | | | | | | | | | | | | | | | 1. Add new surface flags needEquation for client driver use to force the surface tile setting equation compatible. Override 2D/3D macro tile mode to PRT_* tile mode if this flag is TRUE and num slice > 1. 2. Add numEquations and pEquationTable in ADDR_CREATE_OUTPUT structure to return number of equations and the equation table to client driver 3. Add equationIndex in ADDR_COMPUTE_SURFACE_INFO_OUTPUT structure to return the equation index to client driver Please note the use of address equation has following restrictions: 1) The surface can't be splitable 2) The surface can't have non zero tile swizzle value 3) Surface with > 1 slices must have PRT tile mode, which disable slice rotation
* amdgpu/addrlib: style changes and minor cleanupsNicolai Hähnle2017-03-301-6/+6
| | | | Signed-off-by: Nicolai Hähnle <[email protected]>
* amdgpu/addrlib: AddrLib inheritance refactorNicolai Hähnle2017-03-301-2/+2
| | | | | | Add one more abstraction layer into inheritance system. Signed-off-by: Nicolai Hähnle <[email protected]>
* amdgpu/addrlib: Let Kaveri go general stereo right eye offset padding pathXavi Zhang2017-03-301-6/+1
| | | | | | | | Kaveri (2-pipe) macro tiling mode table was initially set to all 4-aspect-ratio so the swizzling path did not work for it and then we chose to pad the offset. We now discover the root cause is that if ratio > 2, the swizzling path does not work. So we can safely use the same path for Kaveri.
* amd/addrlib: move addrlib from amdgpu winsys to common codeDave Airlie2016-09-061-0/+412
Acked-by: Marek Olšák <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-22 06:43:45 +0000