aboutsummaryrefslogtreecommitdiffstats
path: root/src/amd/addrlib/r800/ciaddrlib.cpp
Commit message (Expand)AuthorAgeFilesLines
* amd/addrlib: second update for Vega10 + bug fixesMarek Olšák2017-04-041-39/+71
* amdgpu/addrlib: Seperate 2 dcc related workarounds by different flagsNicolai Hähnle2017-03-301-2/+2
* amdgpu/addrlib: add matchStencilTileCfg and tcCompatible fixesXavi Zhang2017-03-301-14/+126
* amdgpu/addrlib: Adjust bank equation bit order based on macro tile aspect rat...Frans Gu2017-03-301-37/+43
* amdgpu/addrlib: Check prt flag for PRT_THIN1 extra padding for DCC.Xavi Zhang2017-03-301-18/+17
* amdgpu/addrlib: Add new flags minimizePadding and maxBaseAlignFrans Gu2017-03-301-46/+106
* amdgpu/addrlib: Add flag to report if a surface can have dcc ramFrans Gu2017-03-301-1/+24
* amdgpu/addrlib: Fix family setting for VI and CZ ASICsFrans Gu2017-03-301-0/+2
* amdgpu/addrlib: style cleanupNicolai Hähnle2017-03-301-19/+6
* amdgpu/addrlib: Pad pitch to multiples of 256 for DCC surface on FijiNicolai Hähnle2017-03-301-16/+50
* amdgpu/addrlib: Fix number of //Xavi Zhang2017-03-301-2/+2
* amdgpu/addrlib: Cleanup.Nicolai Hähnle2017-03-301-7/+7
* amdgpu/addrlib: Use namespacesXavi Zhang2017-03-301-99/+106
* amdgpu/addrlib: Adjust 99 "*" to 100 "*" alignmentKevin Zhao2017-03-301-65/+65
* amdgpu/addrlib: Add a new tile mode ADDR_TM_UNKNOWNFrans Gu2017-03-301-0/+96
* amdgpu/addrlib: Disable tcComaptible when depth surface is not macro tiledRoy Zhan2017-03-301-17/+20
* amdgpu/addrlib: add equation generationNicolai Hähnle2017-03-301-20/+67
* amdgpu/addrlib: rename ComputeSurfaceThickness to ThicknessNicolai Hähnle2017-03-301-4/+4
* amdgpu/addrlib: Fix invalid access to m_tileTableNicolai Hähnle2017-03-301-6/+17
* amdgpu/addrlib: add tcCompatible htile addr from coordinate support.XiaoYuan Zheng2017-03-301-1/+46
* amdgpu/addrlib: force all zero tile info for linear general.Carlos Xiong2017-03-301-1/+10
* amdgpu/addrlib: Add a member "bpp" for input of method AddrConvertTileIndex a...Nicolai Hähnle2017-03-301-12/+27
* amdgpu/addrlib: Refine the PRT tile mode selectionFrans Gu2017-03-301-49/+19
* amdgpu/addrlib: add dccRamSizeAligned output flagXavi Zhang2017-03-301-0/+5
* amdgpu/addrlib: style changes and minor cleanupsNicolai Hähnle2017-03-301-0/+1
* amdgpu/addrlib: Add GetMaxAlignmentsXavi Zhang2017-03-301-0/+40
* amdgpu/addrlib: Let Kaveri go general stereo right eye offset padding pathXavi Zhang2017-03-301-30/+0
* amdgpu/addrlib: Add a flag "tcCompatible" to surface info output structure.Carlos Xiong2017-03-301-12/+39
* amdgpu/addrlib: add new flag nonSplitXiaoYuan Zheng2017-03-301-1/+1
* amdgpu/addrlib: Change to compute TC compatible stencil infoCarlos Xiong2017-03-301-65/+57
* amdgpu/addrlib: rename SiAddrLib/CiAddrLib to match internal spellingNicolai Hähnle2017-03-301-55/+55
* radeonsi: add Polaris12 support (v3)Junwei Zhang2016-12-211-1/+2
* amd/addrlib: move addrlib from amdgpu winsys to common codeDave Airlie2016-09-061-0/+1831
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-27 13:16:33 +0000