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path: root/src/amd/addrlib/addrinterface.h
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* amd/addrlib: update Mesa's copy of addrlibNicolai Hähnle2018-11-291-3717/+0
* amd/addrlib: update to the latest version for Vega12Marek Olšák2018-03-281-24/+38
* amd/addrlib: update to latest versionMarek Olšák2017-11-081-27/+56
* amd/addrlib: add Addr2IsValidDisplaySwizzleModeMarek Olšák2017-10-121-0/+14
* amd/addrlib: fix typo in api name.Dave Airlie2017-07-171-4/+4
* amd/addrlib: second update for Vega10 + bug fixesMarek Olšák2017-04-041-17/+198
* amd/addrlib: import gfx9 supportNicolai Hähnle2017-03-301-2/+1156
* amd/addrlib: Bump version to 6.02Joe Ma2017-03-301-1/+1
* amdgpu/addrlib: Bump version to 6.01Nicolai Hähnle2017-03-301-2/+2
* amdgpu/addrlib: Seperate 2 dcc related workarounds by different flagsNicolai Hähnle2017-03-301-1/+5
* amdgpu/addrlib: Fix the issue that tcCompatible HTILE slice size is not calcu...Nicolai Hähnle2017-03-301-0/+2
* amdgpu/addrlib: Add a new output flag to notify client that the returned tile...Nicolai Hähnle2017-03-301-1/+4
* amdgpu/addrlib: add matchStencilTileCfg and tcCompatible fixesXavi Zhang2017-03-301-1/+5
* amdgpu/addrlib: Adjust bank equation bit order based on macro tile aspect rat...Frans Gu2017-03-301-2/+5
* amdgpu/addrlib: Add new flags minimizePadding and maxBaseAlignFrans Gu2017-03-301-1/+5
* amdgpu/addrlib: Add flag to report if a surface can have dcc ramFrans Gu2017-03-301-1/+2
* amdgpu/addrlib: Fix number of //Xavi Zhang2017-03-301-16/+16
* amdgpu/addrlib: Adjust 99 "*" to 100 "*" alignmentKevin Zhao2017-03-301-212/+212
* amdgpu/addrlib: Add a new tile mode ADDR_TM_UNKNOWNFrans Gu2017-03-301-1/+2
* amdgpu/addrlib: Add a flag to skip calculate indicesXavi Zhang2017-03-301-1/+2
* amdgpu/addrlib: add equation generationNicolai Hähnle2017-03-301-30/+104
* amdgpu/addrlib: Add new interface to support macro mode index queryFrans Gu2017-03-301-0/+42
* amdgpu/addrlib: add tcCompatible htile addr from coordinate support.XiaoYuan Zheng2017-03-301-0/+3
* amdgpu/addrlib: Add a member "bpp" for input of method AddrConvertTileIndex a...Nicolai Hähnle2017-03-301-0/+2
* amdgpu/addrlib: add dccRamSizeAligned output flagXavi Zhang2017-03-301-1/+2
* amdgpu/addrlib: Change comment alignmentNicolai Hähnle2017-03-301-12/+12
* amdgpu/addrlib: style changes and minor cleanupsNicolai Hähnle2017-03-301-1/+0
* amdgpu/addrlib: add disableLinearOpt flagXavi Zhang2017-03-301-1/+2
* amdgpu/addrlib: Add GetMaxAlignmentsXavi Zhang2017-03-301-0/+26
* amdgpu/addrlib: Rewrite tile mode optmization codeXavi Zhang2017-03-301-4/+2
* amdgpu/addrlib: Add a flag "tcCompatible" to surface info output structure.Carlos Xiong2017-03-301-3/+10
* amdgpu/addrlib: Make comments shorterXavi Zhang2017-03-301-47/+29
* amdgpu/addrlib: add new flag nonSplitXiaoYuan Zheng2017-03-301-1/+2
* amd/addrlib: move addrlib from amdgpu winsys to common codeDave Airlie2016-09-061-0/+2166
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