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* radeonsi: add Polaris PCI IDsSonny Jiang2016-03-241-0/+10
| | | | | | Signed-off-by: Sonny Jiang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> (Polaris10) Reviewed-by: Michel Dänzer <[email protected]> (Polaris11)
* i965/chv: Display proper brandingBen Widawsky2016-03-111-2/+2
| | | | | | | | | | | | | | | | | | | | | | "Braswell" is a Cherryview based *thing*. It unfortunately requires extra information to determine its marketing name. Unlike all previous products, and hopefully all future ones, there is no unique 1:1 mapping of PCI device ID to brand string. I put up a fight about adding any complexity to our GL renderer string code for a very long time. However, a wise man made a comment to me that I couldn't argue with: if a user installs Windows on their hardware, the brand string should be the same as what we display in Linux. The Windows driver apparently does this check, so we should too. Note that I did manage to find a good use for this info anyway in the compute shader thread counts. v2: memcpy instead of strncpy, and some minor changes (Matt) Signed-off-by: Ben Widawsky <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Jordan Justen <[email protected]
* virtio_gpu: Add virtio 1.0 PCI ID to driver mapMarc-André Lureau2016-02-291-0/+1
| | | | | | | | | | | | | Add the virtio-gpu PCI ID for virtio 1.0 (according to the specification, "the PCI Device ID is calculated by adding 0x1040 to the Virtio Device ID") Support for virtio 1.0 was added in qemu 2.4 (same time virtio-gpu landed). Cc: "11.1 11.2" <[email protected]> Signed-off-by: Marc-André Lureau <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* i965/skl: Update Skylake renderer stringsBen Widawsky2016-02-171-9/+9
| | | | | | | | | | Also adds some of the Iris/Pro parts which we previously didn't have named. v2: 0x192d is gt3, not gt4 Adding some 'e' tags for eDRAM parts Signed-off-by: Ben Widawsky <[email protected]> Acked-by: Michał Winiarski <[email protected]>
* i965/skl: Add two missing device IDsBen Widawsky2016-02-171-0/+2
| | | | | | | | | | | | The Iris part is left unbranded because we did not have these with original SKL. v2: 0x192d is gt3, not gt4 v3: Forgot to update the temporary brand string when I did v2. Cc: "11.0 11.1" <[email protected] Signed-off-by: Ben Widawsky <[email protected]> Acked-by: Michał Winiarski <[email protected]>
* virtio_gpu: Add PCI ID to driver mapRob Herring2016-01-231-0/+1
| | | | | | | Add the virtio-gpu PCI ID so the driver probing works. Signed-off-by: Rob Herring <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* mesa: Add KBL PCI IDs and platform information.Sarah Sharp2016-01-061-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | | Add PCI IDs for the Intel Kabylake platforms. The IDs are taken directly from the Linux kernel patches, which are under review: http://lists.freedesktop.org/archives/intel-gfx/2015-October/078967.html http://cgit.freedesktop.org/~vivijim/drm-intel/log/?h=kbl-upstream-v2 The Kabylake PCI IDs taken from the kernel are rearranged to be in order of GT type, then PCI ID. Please note that if this patch is backported, the following fixes will need to be added before this patch: commit 28ed1e08e8ba98e "i965/skl: Remove early platform support" commit c1e38ad37042b0e "i965/skl: Use larger URB size where available." Thanks to Ben for fixing a bug around setting urb.size, and being patient with my questions about what the various fields mean. Signed-off-by: Sarah Sharp <[email protected]> Suggested-by: Ben Widawsky <[email protected]> Tested-by: Rodrigo Vivi <[email protected]> (KBL-GT2) Cc: "11.1" <[email protected]>
* i965/skl: PCI ID cleanup and brand stringsBen Widawsky2015-11-031-15/+19
| | | | | | | | | | | | A few new PCI ids are added here, and one is removed (0x190B) because it no longer seems to exist anywhere. v2-4: Only use ascii characters (Ilia) 0x1921 is no longer marked as f Reviewed-by: Jordan Justen <[email protected]> Signed-off-by: Ben Widawsky <[email protected]>
* i965/skl: Add GT4 PCI IDsBen Widawsky2015-11-031-0/+4
| | | | | | | | | | | | | | | | | | | | Like other gen8+ hardware, the hardware automatically scales up thread counts. We must be careful about the URB sizes since GT4 adds another slice. One of the existing PCI IDs is actually mislabeled as GT3. Arguably this is a real bug since the URB size will be wrong. Because this patch is simply meant to add the missing IDs, that will be fixed in a later patch. v2: No longer relevant. v3: Update the wm thread count to support GT4. The WM thread count is used to determine the maximum scratch space required. Currently the code always allocates the maximum amount even though lower GT SKUs require less. The formula is threads_per_psd * subslices_per_slice * slices Cc: [email protected] Reviewed-by: Jordan Justen <[email protected]> Signed-off-by: Ben Widawsky <[email protected]>
* radeonsi: add Stoney pci idsSamuel Li2015-10-231-0/+2
| | | | | | | Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Michel Dänzer <[email protected]> Signed-off-by: Samuel Li <[email protected]> Cc: [email protected]
* radeonsi: add all new VI PCI IDs including FijiMarek Olšák2015-08-141-0/+24
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* radeonsi: add new OLAND pci idAlex Deucher2015-08-101-0/+1
| | | | | | | Reviewed-by: Edward O'Callaghan <[email protected]> Reviewed-by: Michel Dänzer <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected]
* i965/bxt: Add basic Broxton infrastructureBen Widawsky2015-06-241-0/+3
| | | | | | | | | | | | | | | | | The thread counts and URB information are all speculative numbers that were based on some CHV numbers at the time. v2: Originally this patch had PCI IDs. I've moved that to a new patch at the end of the series. Remove is_cherryview hack. Add PCI ids. These match the ones defined in the kernel. The only one tested by us is 0x0a84. Capitalize the hex string (Mark) Signed-off-by: Ben Widawsky <[email protected]> Tested-by: "Lecluse, Philippe" <[email protected]> Reviewed-by: Mark Janes <[email protected]>
* radeonsi: add new bonaire pci idAlex Deucher2015-05-121-0/+1
| | | | | | Reviewed-by: Marek Olšák <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected]
* i965: Add marketing names for CHVVille Syrjälä2015-04-161-4/+4
| | | | | | | All CHV devices will be branded as "Intel(r) HD Graphics". Reviewed-by: Kenneth Graunke <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]>
* i915: For the love of all that is holy, stop saying "IGD"Adam Jackson2015-02-181-2/+2
| | | | | | | a001 and a011 are pineview chips. Say so. Reviewed-by: Matt Turner <[email protected]> Signed-off-by: Adam Jackson <[email protected]>
* i965/skl: Add Skylake PCI IDsKristian Høgsberg2014-12-081-0/+15
| | | | Signed-off-by: Kristian Høgsberg <[email protected]>
* radeonsi: add new SI pci idsAlex Deucher2014-08-211-0/+4
| | | | | Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected]
* radeonsi: add new CIK pci idsAlex Deucher2014-08-211-0/+3
| | | | | Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected]
* i965: Include marketing names for Broadwell GPUs.Kenneth Graunke2014-06-261-18/+18
| | | | | | | | | | | | | Intel would like us to include the marketing names. Developers additionally want "Broadwell GT1/2/3" because it makes it easier to identify what hardware users have when they request assistance or report issues. Including both makes it easy for everyone to map between the names. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Cc: "10.2" <[email protected]>
* radeonsi: add Mullins pci ids.Samuel Li2014-05-021-0/+17
| | | | | | Signed-off-by: Samuel Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* i965: Add Cherryview support.Kenneth Graunke2014-03-281-0/+4
| | | | | | | | Based on a patch by Ville Syrjälä. As usual, these are placeholder values; actual values will come later. Signed-off-by: Kenneth Graunke <[email protected]>
* loader: add special logic to distinguish nouveau from nouveau_vieuxIlia Mirkin2014-03-191-81/+0
| | | | | | | | | | | There are a lot of different pci ids supported by nouveau, and more are added all the time. The relevant distinguisher between drivers is the chipset id. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Cc: "10.1" <[email protected]>
* i965: Enable Broadwell support.Kenneth Graunke2014-02-201-2/+0
| | | | | Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Add (disabled) Broadwell PCI IDs.Kenneth Graunke2014-01-311-0/+20
| | | | | | | | | This puts the PCI IDs in place so it's easy to enable support. However, it doesn't actually enable support since it's very preliminary still, and a few crucial pieces (such as BLORP) are still missing. Signed-off-by: Kenneth Graunke <[email protected]> Acked-by: Eric Anholt <[email protected]>
* pci_ids: no not include loader.hEmil Velikov2014-01-181-1/+4
| | | | | | | | | | | | | | As per original approach by Rob, each user of the loader lib should include loader.h and the pci_id_driver_map.h header will be used exclusively by the loader. Add back the include guard __IS_LOADER and remove no longer needed include folder in the scons build. Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Rob Clark <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* loader: introduce the loader util libEmil Velikov2014-01-181-13/+11
| | | | | | | | | | | | | | | | | | | | | | All the various window system integration layers duplicate roughly the same code for figuring out device and driver name, pci-id's, etc. Which is sad. So extract it out into a loader util lib. v2 (Emil) * Separate the introduction of libloader from the code de-duplication. * Strip out non-pci devices support. * Add scons + Android build system support. * Add VISIBILITY_CFLAGS to avoid exporting the loader funcs. v3 (Emil) * PIPE_OS_ANDROID is undefined at this scope, use ANDROID * Make sure we define _EGL_NO_DRM when building only swrast Signed-off-by: Rob Clark <[email protected]> Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Rob Clark <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* r600g: fix SUMO2 pci idAlex Deucher2013-12-241-1/+1
| | | | | | | 0x9649 is sumo2, not sumo. Signed-off-by: Alex Deucher <[email protected]> CC: "9.2" "10.0" <[email protected]>
* radeonsi: add Hawaii pci idsAlex Deucher2013-11-151-0/+13
| | | | | Reviewed-by: Michel Dänzer <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* i965: Add the family name to the PCI ID table.Kenneth Graunke2013-10-132-94/+94
| | | | | | | | I removed this a while ago, since we never used it, but I'm finally resurrecting the idea in the next commits. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965: Remove #define name from PCI ID table.Kenneth Graunke2013-10-132-94/+94
| | | | | | | | | | Nothing uses the #define name, and it's not terribly useful - the numerical ID serves the same purpose. The only thing we could really do with it is generate slightly prettier preprocessed code. But who looks at that? Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* radeonsi: add berlin pci idsAlex Deucher2013-09-061-0/+22
| | | | Signed-off-by: Alex Deucher <[email protected]>
* radeonsi: add kabini pci idsAlex Deucher2013-06-281-0/+17
| | | | Signed-off-by: Alex Deucher <[email protected]>
* radeonsi: add bonaire pci idsAlex Deucher2013-06-281-0/+9
| | | | Signed-off-by: Alex Deucher <[email protected]>
* intel: Use the CHIPSET macro in the PCI ID tables for the device name.Kenneth Graunke2013-06-063-110/+110
| | | | | | | | | | | | | Putting the human readable device names directly in the PCI ID list consolidates things in one place. It also makes it easy to customize the name on a per-PCI ID basis without a huge code explosion. Based on a patch by Kristian Høgsberg. v2: Fix 830M/845G names and #undef CHIPSET (caught by Emit Velikov). Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* intel: Remove 'misc' parameter from CHIPSET macro in PCI ID tables.Kenneth Graunke2013-06-063-110/+110
| | | | | | | This has never actually been used for anything. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Adding more reserved PCI IDs for Haswell.Rodrigo Vivi2013-06-051-0/+24
| | | | | | | | | | | At DDX commit Chris mentioned the tendency we have of finding out more PCI IDs only when users report. So Let's add all new reserved Haswell IDs. NOTE: This is a candidate for stable branches. Bugzilla: http://bugs.freedesktop.org/show_bug.cgi?id=63701 Signed-off-by: Rodrigo Vivi <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* radeonsi: add Hainan pci idsAlex Deucher2013-05-141-0/+7
| | | | | | | Note: this is a candidate for the 9.1 branch Signed-off-by: Alex Deucher <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* i965: make GT3 machines work as GT3 instead of GT2Paulo Zanoni2013-05-091-12/+12
| | | | | | | | | | | | | We were not allowed to say the "GT3" name, but we really needed to have the PCI IDs because too many people had such machines, so we had to make the GT3 machines work as GT2. Let's just say that GT2_PLUS was a short for GT2_PLUS_1 :) NOTE: This is a candidate for stable branches. Signed-off-by: Paulo Zanoni <[email protected]> Signed-off-by: Kenneth Graunke <[email protected]>
* radeonsi: add new SI pci idsAlex Deucher2013-04-251-0/+3
| | | | | | Note: this is a candidate for the 9.1 branch. Signed-off-by: Alex Deucher <[email protected]>
* r600g: add new richland pci idsAlex Deucher2013-04-251-0/+2
| | | | | | Note: this is a candidate for the stable branches. Signed-off-by: Alex Deucher <[email protected]>
* i965: Enable the Bay Trail platform.Kenneth Graunke2013-04-161-0/+5
| | | | | | | | This patch adds PCI IDs for Bay Trail (sometimes called Valley View). As far as the 3D driver is concerned, it's very similar to Ivybridge, so the existing code should work just fine. Signed-off-by: Kenneth Graunke <[email protected]>
* r600g: add Richland APU pci idsAlex Deucher2013-03-151-0/+11
| | | | | | Note: this is a candidate for the stable branches. Signed-off-by: Alex Deucher <[email protected]>
* i965: Fix Crystal Well PCI IDs.Kenneth Graunke2013-03-031-9/+9
| | | | | | | | | The second digit was off by one, which meant we accidentally treated GTn as GT(n-1). This also meant no support for GT1 at all. NOTE: This is a candidate for stable branches. Signed-off-by: Kenneth Graunke <[email protected]>
* radeonsi: add Oland pci idsAlex Deucher2013-02-041-0/+14
| | | | | | Signed-off-by: Alex Deucher <[email protected]> Note: this is a candidate for the 9.1 branch.
* radeonsi: add a new SI pci idAlex Deucher2012-11-211-0/+1
| | | | | | Note: this is a candidate for the stable branch. Signed-off-by: Alex Deucher <[email protected]>
* radeonsi: add some new SI pci idsAlex Deucher2012-10-161-0/+3
| | | | | | Note: this is a candidate for the stable branch. Signed-off-by: Alex Deucher <[email protected]>
* i965: add more Haswell PCI IDsPaulo Zanoni2012-08-071-1/+32
| | | | | | Signed-off-by: Paulo Zanoni <[email protected]> Reviewed-by: Rodrigo Vivi <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* radeonsi: add some new pci idsAlex Deucher2012-08-061-0/+3
| | | | Signed-off-by: Alex Deucher <[email protected]>
* r600g: add additional evergreen pci idsAlex Deucher2012-08-061-0/+3
| | | | | | Note: this is a candidate for the stable branches. Signed-off-by: Alex Deucher <[email protected]>
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