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* Revert "intel: Remove unused Kabylake pci idsAnuj Phogat2017-09-211-0/+8
| | | | | | | | | | | | drm-intel is in favor of keeping the unused pci-id's which are still listed in the h/w specs. To keep it uniform across multiple gfx stack components, I'm reverting below Mesa patches: b2dae9f8fd310c19e66b161a7ee9845af78f73e0 ebc5ccf3cc88990248695e833d9ff11e10d91240. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Rodrigo Vivi <[email protected]>
* intel: Remove unused Kabylake pci idAnuj Phogat2017-09-111-1/+0
| | | | | | | I missed this one in Mesa commit ebc5ccf. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* intel: Add brand string for KBL-RAnuj Phogat2017-09-061-1/+1
| | | | | Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* intel: Change a KBL pci id to GT2 from GT1.5Anuj Phogat2017-09-061-1/+1
| | | | | Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* intel: Fix few KBL brand stringsAnuj Phogat2017-09-061-2/+2
| | | | | Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* intel: Remove unused Kabylake pci idsAnuj Phogat2017-09-061-7/+0
| | | | | | | These PCI IDs are not used in any Kabylake SKUs. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965/CFL: Add PCI Ids for Coffee Lake.Anusha Srivatsa2017-06-221-0/+11
| | | | | | | | | | | | | | Coffee Lake has a gen9 graphics following KBL. From 3D perspective, CFL is a clone of KBL/SKL features. v2: Change commit message, correct alignment <Anuj Phogat> v3: Update IDs. v4: Initialize l3_banks, correct nomenclature <Anuj> Cc: Rodrigo Vivi <[email protected]> Signed-off-by: Anusha Srivatsa <[email protected]> Acked-by: Benjamin Widawsky <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* radeonsi: add new polaris12 pci idAlex Deucher2017-06-161-0/+1
| | | | | | Reviewed-by: Marek Olšák <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: 17.0 17.1 <[email protected]>
* i965/cnl: Add a preliminary device for CannonlakeBen Widawsky2017-06-091-0/+12
| | | | | | | | | | | | | | | | v2 (Anuj): Rebased on master and updated pci ids Remove redundant initialization of max_wm_threads to 64 * 12. For gen9+ max_wm_threads are initialized in gen_get_device_info(). v3 (Anuj): Move the patch to end of series. Remove unused gt1, gt2, gt3 functions. Remove l3_banks variable. Variable is now available on master. Signed-off-by: Anuj Phogat <[email protected]> Signed-off-by: Ben Widawsky <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* radeonsi/gfx9: add support for RavenMarek Olšák2017-05-151-0/+2
| | | | | | Cc: 17.1 <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: add new vega10 pci idsAlex Deucher2017-05-101-0/+2
| | | | | | Reviewed-by: Nicolai Hähnle <[email protected]> Cc: 17.1 <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* radeonsi: add new polaris10 pci idAlex Deucher2017-04-051-0/+1
| | | | | | Reviewed-by: Christian König <[email protected]> Cc: 13.0 17.0 <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* radeonsi: add Vega10 PCI IDsMarek Olšák2017-03-301-0/+8
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: add new polaris12 pci idAlex Deucher2017-03-171-0/+1
| | | | | | Reviewed-by: Marek Olšák <[email protected]> Cc: 17.0 <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* i965: Add Kaby Lake brandstringsBen Widawsky2017-03-021-10/+10
| | | | | | | | While here, use the spacing defined in Ark. https://ark.intel.com/products/codename/82879/Kaby-Lake Reviewed-by: Jason Ekstrand <[email protected]> Signed-off-by: Ben Widawsky <[email protected]>
* radeonsi: add Polaris12 PCI IDJunwei Zhang2016-12-211-0/+7
| | | | | | Reviewed-by: Marek Olšák <[email protected]> Signed-off-by: Junwei Zhang <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* i965: Fix KBL typo in stringBen Widawsky2016-11-151-1/+1
| | | | | | Signed-off-by: Ben Widawsky <[email protected]> Reviewed-by: Anuj Phogat <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/glk: Add basic Geminilake supportBen Widawsky2016-11-151-0/+2
| | | | | | | | | | v2: s/bdw/gen; Add the 2x6 config v3: Add min_ds_entries Cc: "13.0" <[email protected]> Signed-off-by: Ben Widawsky <[email protected]> Reviewed-by: Anuj Phogat <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Reorder PCI ID list to match release orderBen Widawsky2016-10-201-9/+9
| | | | | | | I have some OCD... Signed-off-by: Ben Widawsky <[email protected]> Reviewed-by: Dylan Baker <[email protected]>
* i965: Add some APL and KBL SKU stringsBen Widawsky2016-10-201-4/+4
| | | | | | | We got a couple for products that exist on ark.intel.com, so let's just put them in now. Signed-off-by: Ben Widawsky <[email protected]>
* i965: Removing PCI IDs that are no longer listed as Kabylake.Rodrigo Vivi2016-06-291-5/+0
| | | | | | | | | | | | | | | | This is unusual. Usually IDs listed on early stages of platform definition are kept there as reserved for later use. However these IDs here are not listed anymore in any of steppings and devices IDs tables for Kabylake on configurations overview section of BSpec. So it is better removing them before they become used in any other future platform. Reviewed-by: Dhinakaran Pandiyan <[email protected]> Acked-by: Kenneth Graunke <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]>
* i956: Add more Kabylake PCI IDs.Rodrigo Vivi2016-06-291-0/+3
| | | | | | | | The spec has been updated adding new PCI IDs. Reviewed-by: Dhinakaran Pandiyan <[email protected]> Acked-by: Kenneth Graunke <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]>
* i965/bxt: Add 2x6 variantBen Widawsky2016-05-261-0/+2
| | | | | | Cc: [email protected] Signed-off-by: Ben Widawsky <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* radeonsi: add new polaris11 pci idsAlex Deucher2016-05-171-0/+3
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* radeonsi: add new polaris10 pci idsAlex Deucher2016-05-171-0/+9
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* radeonsi: add Polaris PCI IDsSonny Jiang2016-03-241-0/+10
| | | | | | Signed-off-by: Sonny Jiang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> (Polaris10) Reviewed-by: Michel Dänzer <[email protected]> (Polaris11)
* i965/chv: Display proper brandingBen Widawsky2016-03-111-2/+2
| | | | | | | | | | | | | | | | | | | | | | "Braswell" is a Cherryview based *thing*. It unfortunately requires extra information to determine its marketing name. Unlike all previous products, and hopefully all future ones, there is no unique 1:1 mapping of PCI device ID to brand string. I put up a fight about adding any complexity to our GL renderer string code for a very long time. However, a wise man made a comment to me that I couldn't argue with: if a user installs Windows on their hardware, the brand string should be the same as what we display in Linux. The Windows driver apparently does this check, so we should too. Note that I did manage to find a good use for this info anyway in the compute shader thread counts. v2: memcpy instead of strncpy, and some minor changes (Matt) Signed-off-by: Ben Widawsky <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Jordan Justen <[email protected]
* virtio_gpu: Add virtio 1.0 PCI ID to driver mapMarc-André Lureau2016-02-291-0/+1
| | | | | | | | | | | | | Add the virtio-gpu PCI ID for virtio 1.0 (according to the specification, "the PCI Device ID is calculated by adding 0x1040 to the Virtio Device ID") Support for virtio 1.0 was added in qemu 2.4 (same time virtio-gpu landed). Cc: "11.1 11.2" <[email protected]> Signed-off-by: Marc-André Lureau <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* i965/skl: Update Skylake renderer stringsBen Widawsky2016-02-171-9/+9
| | | | | | | | | | Also adds some of the Iris/Pro parts which we previously didn't have named. v2: 0x192d is gt3, not gt4 Adding some 'e' tags for eDRAM parts Signed-off-by: Ben Widawsky <[email protected]> Acked-by: Michał Winiarski <[email protected]>
* i965/skl: Add two missing device IDsBen Widawsky2016-02-171-0/+2
| | | | | | | | | | | | The Iris part is left unbranded because we did not have these with original SKL. v2: 0x192d is gt3, not gt4 v3: Forgot to update the temporary brand string when I did v2. Cc: "11.0 11.1" <[email protected] Signed-off-by: Ben Widawsky <[email protected]> Acked-by: Michał Winiarski <[email protected]>
* virtio_gpu: Add PCI ID to driver mapRob Herring2016-01-231-0/+1
| | | | | | | Add the virtio-gpu PCI ID so the driver probing works. Signed-off-by: Rob Herring <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* mesa: Add KBL PCI IDs and platform information.Sarah Sharp2016-01-061-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | | Add PCI IDs for the Intel Kabylake platforms. The IDs are taken directly from the Linux kernel patches, which are under review: http://lists.freedesktop.org/archives/intel-gfx/2015-October/078967.html http://cgit.freedesktop.org/~vivijim/drm-intel/log/?h=kbl-upstream-v2 The Kabylake PCI IDs taken from the kernel are rearranged to be in order of GT type, then PCI ID. Please note that if this patch is backported, the following fixes will need to be added before this patch: commit 28ed1e08e8ba98e "i965/skl: Remove early platform support" commit c1e38ad37042b0e "i965/skl: Use larger URB size where available." Thanks to Ben for fixing a bug around setting urb.size, and being patient with my questions about what the various fields mean. Signed-off-by: Sarah Sharp <[email protected]> Suggested-by: Ben Widawsky <[email protected]> Tested-by: Rodrigo Vivi <[email protected]> (KBL-GT2) Cc: "11.1" <[email protected]>
* i965/skl: PCI ID cleanup and brand stringsBen Widawsky2015-11-031-15/+19
| | | | | | | | | | | | A few new PCI ids are added here, and one is removed (0x190B) because it no longer seems to exist anywhere. v2-4: Only use ascii characters (Ilia) 0x1921 is no longer marked as f Reviewed-by: Jordan Justen <[email protected]> Signed-off-by: Ben Widawsky <[email protected]>
* i965/skl: Add GT4 PCI IDsBen Widawsky2015-11-031-0/+4
| | | | | | | | | | | | | | | | | | | | Like other gen8+ hardware, the hardware automatically scales up thread counts. We must be careful about the URB sizes since GT4 adds another slice. One of the existing PCI IDs is actually mislabeled as GT3. Arguably this is a real bug since the URB size will be wrong. Because this patch is simply meant to add the missing IDs, that will be fixed in a later patch. v2: No longer relevant. v3: Update the wm thread count to support GT4. The WM thread count is used to determine the maximum scratch space required. Currently the code always allocates the maximum amount even though lower GT SKUs require less. The formula is threads_per_psd * subslices_per_slice * slices Cc: [email protected] Reviewed-by: Jordan Justen <[email protected]> Signed-off-by: Ben Widawsky <[email protected]>
* radeonsi: add Stoney pci idsSamuel Li2015-10-231-0/+2
| | | | | | | Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Michel Dänzer <[email protected]> Signed-off-by: Samuel Li <[email protected]> Cc: [email protected]
* radeonsi: add all new VI PCI IDs including FijiMarek Olšák2015-08-141-0/+24
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* radeonsi: add new OLAND pci idAlex Deucher2015-08-101-0/+1
| | | | | | | Reviewed-by: Edward O'Callaghan <[email protected]> Reviewed-by: Michel Dänzer <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected]
* i965/bxt: Add basic Broxton infrastructureBen Widawsky2015-06-241-0/+3
| | | | | | | | | | | | | | | | | The thread counts and URB information are all speculative numbers that were based on some CHV numbers at the time. v2: Originally this patch had PCI IDs. I've moved that to a new patch at the end of the series. Remove is_cherryview hack. Add PCI ids. These match the ones defined in the kernel. The only one tested by us is 0x0a84. Capitalize the hex string (Mark) Signed-off-by: Ben Widawsky <[email protected]> Tested-by: "Lecluse, Philippe" <[email protected]> Reviewed-by: Mark Janes <[email protected]>
* radeonsi: add new bonaire pci idAlex Deucher2015-05-121-0/+1
| | | | | | Reviewed-by: Marek Olšák <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected]
* i965: Add marketing names for CHVVille Syrjälä2015-04-161-4/+4
| | | | | | | All CHV devices will be branded as "Intel(r) HD Graphics". Reviewed-by: Kenneth Graunke <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]>
* i915: For the love of all that is holy, stop saying "IGD"Adam Jackson2015-02-181-2/+2
| | | | | | | a001 and a011 are pineview chips. Say so. Reviewed-by: Matt Turner <[email protected]> Signed-off-by: Adam Jackson <[email protected]>
* i965/skl: Add Skylake PCI IDsKristian Høgsberg2014-12-081-0/+15
| | | | Signed-off-by: Kristian Høgsberg <[email protected]>
* radeonsi: add new SI pci idsAlex Deucher2014-08-211-0/+4
| | | | | Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected]
* radeonsi: add new CIK pci idsAlex Deucher2014-08-211-0/+3
| | | | | Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected]
* i965: Include marketing names for Broadwell GPUs.Kenneth Graunke2014-06-261-18/+18
| | | | | | | | | | | | | Intel would like us to include the marketing names. Developers additionally want "Broadwell GT1/2/3" because it makes it easier to identify what hardware users have when they request assistance or report issues. Including both makes it easy for everyone to map between the names. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Cc: "10.2" <[email protected]>
* radeonsi: add Mullins pci ids.Samuel Li2014-05-021-0/+17
| | | | | | Signed-off-by: Samuel Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* i965: Add Cherryview support.Kenneth Graunke2014-03-281-0/+4
| | | | | | | | Based on a patch by Ville Syrjälä. As usual, these are placeholder values; actual values will come later. Signed-off-by: Kenneth Graunke <[email protected]>
* loader: add special logic to distinguish nouveau from nouveau_vieuxIlia Mirkin2014-03-191-81/+0
| | | | | | | | | | | There are a lot of different pci ids supported by nouveau, and more are added all the time. The relevant distinguisher between drivers is the chipset id. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Cc: "10.1" <[email protected]>
* i965: Enable Broadwell support.Kenneth Graunke2014-02-201-2/+0
| | | | | Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Add (disabled) Broadwell PCI IDs.Kenneth Graunke2014-01-311-0/+20
| | | | | | | | | This puts the PCI IDs in place so it's easy to enable support. However, it doesn't actually enable support since it's very preliminary still, and a few crucial pieces (such as BLORP) are still missing. Signed-off-by: Kenneth Graunke <[email protected]> Acked-by: Eric Anholt <[email protected]>
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