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* i965/skl: PCI ID cleanup and brand stringsBen Widawsky2015-11-031-15/+19
| | | | | | | | | | | | A few new PCI ids are added here, and one is removed (0x190B) because it no longer seems to exist anywhere. v2-4: Only use ascii characters (Ilia) 0x1921 is no longer marked as f Reviewed-by: Jordan Justen <[email protected]> Signed-off-by: Ben Widawsky <[email protected]>
* i965/skl: Add GT4 PCI IDsBen Widawsky2015-11-031-0/+4
| | | | | | | | | | | | | | | | | | | | Like other gen8+ hardware, the hardware automatically scales up thread counts. We must be careful about the URB sizes since GT4 adds another slice. One of the existing PCI IDs is actually mislabeled as GT3. Arguably this is a real bug since the URB size will be wrong. Because this patch is simply meant to add the missing IDs, that will be fixed in a later patch. v2: No longer relevant. v3: Update the wm thread count to support GT4. The WM thread count is used to determine the maximum scratch space required. Currently the code always allocates the maximum amount even though lower GT SKUs require less. The formula is threads_per_psd * subslices_per_slice * slices Cc: [email protected] Reviewed-by: Jordan Justen <[email protected]> Signed-off-by: Ben Widawsky <[email protected]>
* radeonsi: add Stoney pci idsSamuel Li2015-10-231-0/+2
| | | | | | | Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Michel Dänzer <[email protected]> Signed-off-by: Samuel Li <[email protected]> Cc: [email protected]
* radeonsi: add all new VI PCI IDs including FijiMarek Olšák2015-08-141-0/+24
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* radeonsi: add new OLAND pci idAlex Deucher2015-08-101-0/+1
| | | | | | | Reviewed-by: Edward O'Callaghan <[email protected]> Reviewed-by: Michel Dänzer <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected]
* i965/bxt: Add basic Broxton infrastructureBen Widawsky2015-06-241-0/+3
| | | | | | | | | | | | | | | | | The thread counts and URB information are all speculative numbers that were based on some CHV numbers at the time. v2: Originally this patch had PCI IDs. I've moved that to a new patch at the end of the series. Remove is_cherryview hack. Add PCI ids. These match the ones defined in the kernel. The only one tested by us is 0x0a84. Capitalize the hex string (Mark) Signed-off-by: Ben Widawsky <[email protected]> Tested-by: "Lecluse, Philippe" <[email protected]> Reviewed-by: Mark Janes <[email protected]>
* radeonsi: add new bonaire pci idAlex Deucher2015-05-121-0/+1
| | | | | | Reviewed-by: Marek Olšák <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected]
* i965: Add marketing names for CHVVille Syrjälä2015-04-161-4/+4
| | | | | | | All CHV devices will be branded as "Intel(r) HD Graphics". Reviewed-by: Kenneth Graunke <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]>
* i915: For the love of all that is holy, stop saying "IGD"Adam Jackson2015-02-181-2/+2
| | | | | | | a001 and a011 are pineview chips. Say so. Reviewed-by: Matt Turner <[email protected]> Signed-off-by: Adam Jackson <[email protected]>
* i965/skl: Add Skylake PCI IDsKristian Høgsberg2014-12-081-0/+15
| | | | Signed-off-by: Kristian Høgsberg <[email protected]>
* radeonsi: add new SI pci idsAlex Deucher2014-08-211-0/+4
| | | | | Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected]
* radeonsi: add new CIK pci idsAlex Deucher2014-08-211-0/+3
| | | | | Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected]
* i965: Include marketing names for Broadwell GPUs.Kenneth Graunke2014-06-261-18/+18
| | | | | | | | | | | | | Intel would like us to include the marketing names. Developers additionally want "Broadwell GT1/2/3" because it makes it easier to identify what hardware users have when they request assistance or report issues. Including both makes it easy for everyone to map between the names. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Cc: "10.2" <[email protected]>
* radeonsi: add Mullins pci ids.Samuel Li2014-05-021-0/+17
| | | | | | Signed-off-by: Samuel Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* i965: Add Cherryview support.Kenneth Graunke2014-03-281-0/+4
| | | | | | | | Based on a patch by Ville Syrjälä. As usual, these are placeholder values; actual values will come later. Signed-off-by: Kenneth Graunke <[email protected]>
* loader: add special logic to distinguish nouveau from nouveau_vieuxIlia Mirkin2014-03-191-81/+0
| | | | | | | | | | | There are a lot of different pci ids supported by nouveau, and more are added all the time. The relevant distinguisher between drivers is the chipset id. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Cc: "10.1" <[email protected]>
* i965: Enable Broadwell support.Kenneth Graunke2014-02-201-2/+0
| | | | | Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Add (disabled) Broadwell PCI IDs.Kenneth Graunke2014-01-311-0/+20
| | | | | | | | | This puts the PCI IDs in place so it's easy to enable support. However, it doesn't actually enable support since it's very preliminary still, and a few crucial pieces (such as BLORP) are still missing. Signed-off-by: Kenneth Graunke <[email protected]> Acked-by: Eric Anholt <[email protected]>
* pci_ids: no not include loader.hEmil Velikov2014-01-181-1/+4
| | | | | | | | | | | | | | As per original approach by Rob, each user of the loader lib should include loader.h and the pci_id_driver_map.h header will be used exclusively by the loader. Add back the include guard __IS_LOADER and remove no longer needed include folder in the scons build. Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Rob Clark <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* loader: introduce the loader util libEmil Velikov2014-01-181-13/+11
| | | | | | | | | | | | | | | | | | | | | | All the various window system integration layers duplicate roughly the same code for figuring out device and driver name, pci-id's, etc. Which is sad. So extract it out into a loader util lib. v2 (Emil) * Separate the introduction of libloader from the code de-duplication. * Strip out non-pci devices support. * Add scons + Android build system support. * Add VISIBILITY_CFLAGS to avoid exporting the loader funcs. v3 (Emil) * PIPE_OS_ANDROID is undefined at this scope, use ANDROID * Make sure we define _EGL_NO_DRM when building only swrast Signed-off-by: Rob Clark <[email protected]> Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Rob Clark <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* r600g: fix SUMO2 pci idAlex Deucher2013-12-241-1/+1
| | | | | | | 0x9649 is sumo2, not sumo. Signed-off-by: Alex Deucher <[email protected]> CC: "9.2" "10.0" <[email protected]>
* radeonsi: add Hawaii pci idsAlex Deucher2013-11-151-0/+13
| | | | | Reviewed-by: Michel Dänzer <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* i965: Add the family name to the PCI ID table.Kenneth Graunke2013-10-132-94/+94
| | | | | | | | I removed this a while ago, since we never used it, but I'm finally resurrecting the idea in the next commits. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965: Remove #define name from PCI ID table.Kenneth Graunke2013-10-132-94/+94
| | | | | | | | | | Nothing uses the #define name, and it's not terribly useful - the numerical ID serves the same purpose. The only thing we could really do with it is generate slightly prettier preprocessed code. But who looks at that? Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* radeonsi: add berlin pci idsAlex Deucher2013-09-061-0/+22
| | | | Signed-off-by: Alex Deucher <[email protected]>
* radeonsi: add kabini pci idsAlex Deucher2013-06-281-0/+17
| | | | Signed-off-by: Alex Deucher <[email protected]>
* radeonsi: add bonaire pci idsAlex Deucher2013-06-281-0/+9
| | | | Signed-off-by: Alex Deucher <[email protected]>
* intel: Use the CHIPSET macro in the PCI ID tables for the device name.Kenneth Graunke2013-06-063-110/+110
| | | | | | | | | | | | | Putting the human readable device names directly in the PCI ID list consolidates things in one place. It also makes it easy to customize the name on a per-PCI ID basis without a huge code explosion. Based on a patch by Kristian Høgsberg. v2: Fix 830M/845G names and #undef CHIPSET (caught by Emit Velikov). Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* intel: Remove 'misc' parameter from CHIPSET macro in PCI ID tables.Kenneth Graunke2013-06-063-110/+110
| | | | | | | This has never actually been used for anything. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Adding more reserved PCI IDs for Haswell.Rodrigo Vivi2013-06-051-0/+24
| | | | | | | | | | | At DDX commit Chris mentioned the tendency we have of finding out more PCI IDs only when users report. So Let's add all new reserved Haswell IDs. NOTE: This is a candidate for stable branches. Bugzilla: http://bugs.freedesktop.org/show_bug.cgi?id=63701 Signed-off-by: Rodrigo Vivi <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* radeonsi: add Hainan pci idsAlex Deucher2013-05-141-0/+7
| | | | | | | Note: this is a candidate for the 9.1 branch Signed-off-by: Alex Deucher <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* i965: make GT3 machines work as GT3 instead of GT2Paulo Zanoni2013-05-091-12/+12
| | | | | | | | | | | | | We were not allowed to say the "GT3" name, but we really needed to have the PCI IDs because too many people had such machines, so we had to make the GT3 machines work as GT2. Let's just say that GT2_PLUS was a short for GT2_PLUS_1 :) NOTE: This is a candidate for stable branches. Signed-off-by: Paulo Zanoni <[email protected]> Signed-off-by: Kenneth Graunke <[email protected]>
* radeonsi: add new SI pci idsAlex Deucher2013-04-251-0/+3
| | | | | | Note: this is a candidate for the 9.1 branch. Signed-off-by: Alex Deucher <[email protected]>
* r600g: add new richland pci idsAlex Deucher2013-04-251-0/+2
| | | | | | Note: this is a candidate for the stable branches. Signed-off-by: Alex Deucher <[email protected]>
* i965: Enable the Bay Trail platform.Kenneth Graunke2013-04-161-0/+5
| | | | | | | | This patch adds PCI IDs for Bay Trail (sometimes called Valley View). As far as the 3D driver is concerned, it's very similar to Ivybridge, so the existing code should work just fine. Signed-off-by: Kenneth Graunke <[email protected]>
* r600g: add Richland APU pci idsAlex Deucher2013-03-151-0/+11
| | | | | | Note: this is a candidate for the stable branches. Signed-off-by: Alex Deucher <[email protected]>
* i965: Fix Crystal Well PCI IDs.Kenneth Graunke2013-03-031-9/+9
| | | | | | | | | The second digit was off by one, which meant we accidentally treated GTn as GT(n-1). This also meant no support for GT1 at all. NOTE: This is a candidate for stable branches. Signed-off-by: Kenneth Graunke <[email protected]>
* radeonsi: add Oland pci idsAlex Deucher2013-02-041-0/+14
| | | | | | Signed-off-by: Alex Deucher <[email protected]> Note: this is a candidate for the 9.1 branch.
* radeonsi: add a new SI pci idAlex Deucher2012-11-211-0/+1
| | | | | | Note: this is a candidate for the stable branch. Signed-off-by: Alex Deucher <[email protected]>
* radeonsi: add some new SI pci idsAlex Deucher2012-10-161-0/+3
| | | | | | Note: this is a candidate for the stable branch. Signed-off-by: Alex Deucher <[email protected]>
* i965: add more Haswell PCI IDsPaulo Zanoni2012-08-071-1/+32
| | | | | | Signed-off-by: Paulo Zanoni <[email protected]> Reviewed-by: Rodrigo Vivi <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* radeonsi: add some new pci idsAlex Deucher2012-08-061-0/+3
| | | | Signed-off-by: Alex Deucher <[email protected]>
* r600g: add additional evergreen pci idsAlex Deucher2012-08-061-0/+3
| | | | | | Note: this is a candidate for the stable branches. Signed-off-by: Alex Deucher <[email protected]>
* r600g: add new Trinity PCI idsAlex Deucher2012-06-051-0/+17
| | | | Signed-off-by: Alex Deucher <[email protected]>
* r600g: add new Sumo, Palm, BTC pci idsAlex Deucher2012-06-051-0/+5
| | | | | | Note this is a candidate for the stable branch. Signed-off-by: Alex Deucher <[email protected]>
* radeonsi: add new SI pci idsAlex Deucher2012-06-051-5/+6
| | | | Signed-off-by: Alex Deucher <[email protected]>
* radeonsi: initial WIP SI codeTom Stellard2012-04-132-0/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit adds initial support for acceleration on SI chips. egltri is starting to work. The SI/R600 llvm backend is currently included in mesa but that may change in the future. The plan is to write a single gallium driver and use gallium to support X acceleration. This commit contains patches from: Tom Stellard <[email protected]> Michel Dänzer <[email protected]> Alex Deucher <[email protected]> Vadim Girlin <[email protected]> Signed-off-by: Alex Deucher <[email protected]> The following commits were squashed in: ====================================================================== radeonsi: Remove unused winsys pointer This was removed from r600g in commit: commit 96d882939d612fcc8332f107befec470ed4359de Author: Marek Olšák <[email protected]> Date: Fri Feb 17 01:49:49 2012 +0100 gallium: remove unused winsys pointers in pipe_screen and pipe_context A winsys is already a private object of a driver. ====================================================================== radeonsi: Copy color clamping CAPs from r600 Not sure if the values of these CAPS are correct for radeonsi, but the same changed were made to r600g in commit: commit bc1c8369384b5e16547c5bf9728aa78f8dfd66cc Author: Marek Olšák <[email protected]> Date: Mon Jan 23 03:11:17 2012 +0100 st/mesa: do vertex and fragment color clamping in shaders For ARB_color_buffer_float. Most hardware can't do it and st/mesa is the perfect place for a fallback. The exceptions are: - r500 (vertex clamp only) - nv50 (both) - nvc0 (both) - softpipe (both) We also have to take into account that r300 can do CLAMPED vertex colors only, while r600 can do UNCLAMPED vertex colors only. The difference can be expressed with the two new CAPs. ====================================================================== radeonsi: Remove PIPE_CAP_OUTPUT_READ This CAP was dropped in commit: commit 04e324008759282728a95a1394bac2c4c2a1a3f9 Author: Marek Olšák <[email protected]> Date: Thu Feb 23 23:44:36 2012 +0100 gallium: remove PIPE_SHADER_CAP_OUTPUT_READ r600g is the only driver which has made use of it. The reason the CAP was added was to fix some piglit tests when the GLSL pass lower_output_reads didn't exist. However, not removing output reads breaks the fallback for glClampColorARB, which assumes outputs are not readable. The fix would be non-trivial and my personal preference is to remove the CAP, considering that reading outputs is uncommon and that we can now use lower_output_reads to fix the issue that the CAP was supposed to workaround in the first place. ====================================================================== radeonsi: Add missing parameters to rws->buffer_get_tiling() call This was changed in commit: commit c0c979eebc076b95cc8d18a013ce2968fe6311ad Author: Jerome Glisse <[email protected]> Date: Mon Jan 30 17:22:13 2012 -0500 r600g: add support for common surface allocator for tiling v13 Tiled surface have all kind of alignment constraint that needs to be met. Instead of having all this code duplicated btw ddx and mesa use common code in libdrm_radeon this also ensure that both ddx and mesa compute those alignment in the same way. v2 fix evergreen v3 fix compressed texture and workaround cube texture issue by disabling 2D array mode for cubemap (need to check if r7xx and newer are also affected by the issue) v4 fix texture array v5 fix evergreen and newer, split surface values computation from mipmap tree generation so that we can get them directly from the ddx v6 final fix to evergreen tile split value v7 fix mipmap offset to avoid to use random value, use color view depth view to address different layer as hardware is doing some magic rotation depending on the layer v8 fix COLOR_VIEW on r6xx for linear array mode, use COLOR_VIEW on evergreen, align bytes per pixel to a multiple of a dword v9 fix handling of stencil on evergreen, half fix for compressed texture v10 fix evergreen compressed texture proper support for stencil tile split. Fix stencil issue when array mode was clear by the kernel, always program stencil bo. On evergreen depth buffer bo need to be big enough to hold depth buffer + stencil buffer as even with stencil disabled things get written there. v11 rebase on top of mesa, fix pitch issue with 1d surface on evergreen, old ddx overestimate those. Fix linear case when pitch*height < 64. Fix r300g. v12 Fix linear case when pitch*height < 64 for old path, adapt to libdrm API change v13 add libdrm check Signed-off-by: Jerome Glisse <[email protected]> ====================================================================== radeonsi: Remove PIPE_TRANSFER_MAP_PERMANENTLY This was removed in commit: commit 62f44f670bb0162e89fd4786af877f8da9ff607c Author: Marek Olšák <[email protected]> Date: Mon Mar 5 13:45:00 2012 +0100 Revert "gallium: add flag PIPE_TRANSFER_MAP_PERMANENTLY" This reverts commit 0950086376b1c8b7fb89eda81ed7f2f06dee58bc. It was decided to refactor the transfer API instead of adding workarounds to address the performance issues. ====================================================================== radeonsi: Handle PIPE_VIDEO_CAP_PREFERED_FORMAT. Reintroduced in commit 9d9afcb5bac2931d4b8e6d1aa571e941c5110c90. ====================================================================== radeonsi: nuke the fallback for vertex and fragment color clamping Ported from r600g commit c2b800cf38b299c1ab1c53dc0e4ea00c7acef853. ====================================================================== radeonsi: don't expose transform_feedback2 without kernel support Ported from r600g commit 15146fd1bcbb08e44a1cbb984440ee1a5de63d48. ====================================================================== radeonsi: Handle PIPE_CAP_GLSL_FEATURE_LEVEL. Ported from r600g part of commit 171be755223d99f8cc5cc1bdaf8bd7b4caa04b4f. ====================================================================== radeonsi: set minimum point size to 1.0 for non-sprite non-aa points. Ported from r600g commit f183cc9ce3ad1d043bdf8b38fd519e8f437714fc. ====================================================================== radeonsi: rework and consolidate stencilref state setting. Ported from r600g commit a2361946e782b57f0c63587841ca41c0ea707070. ====================================================================== radeonsi: cleanup setting DB_SHADER_CONTROL. Ported from r600g commit 3d061caaed13b646ff40754f8ebe73f3d4983c5b. ====================================================================== radeonsi: Get rid of register masks. Ported from r600g commits 3d061caaed13b646ff40754f8ebe73f3d4983c5b..9344ab382a1765c1a7c2560e771485edf4954fe2. ====================================================================== radeonsi: get rid of r600_context_reg. Ported from r600g commits 9344ab382a1765c1a7c2560e771485edf4954fe2..bed20f02a771f43e1c5092254705701c228cfa7f. ====================================================================== radeonsi: Fix regression from 'Get rid of register masks'. ====================================================================== radeonsi: optimize r600_resource_va. Ported from r600g commit 669d8766ff3403938794eb80d7769347b6e52174. ====================================================================== radeonsi: remove u8,u16,u32,u64 types. Ported from r600g commit 78293b99b23268e6698f1267aaf40647c17d95a5. ====================================================================== radeonsi: merge r600_context with r600_pipe_context. Ported from r600g commit e4340c1908a6a3b09e1a15d5195f6da7d00494d0. ====================================================================== radeonsi: Miscellaneous context cleanups. Ported from r600g commits e4340c1908a6a3b09e1a15d5195f6da7d00494d0..621e0db71c5ddcb379171064a4f720c9cf01e888. ====================================================================== radeonsi: add a new simple API for state emission. Ported from r600g commits 621e0db71c5ddcb379171064a4f720c9cf01e888..f661405637bba32c2cfbeecf6e2e56e414e9521e. ====================================================================== radeonsi: Also remove sbu_flags member of struct r600_reg. Requires using sid.h instead of r600d.h for the new CP_COHER_CNTL definitions, so some code needs to be disabled for now. ====================================================================== radeonsi: Miscellaneous simplifications. Ported from r600g commits 38bf2763482b4f1b6d95cd51aecec75601d8b90f and b0337b679ad4c2feae59215104cfa60b58a619d5. ====================================================================== radeonsi: Handle PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION. Ported from commit 8b4f7b0672d663273310fffa9490ad996f5b914a. ====================================================================== radeonsi: Use a fake reloc to sleep for fences. Ported from r600g commit 8cd03b933cf868ff867e2db4a0937005a02fd0e4. ====================================================================== radeonsi: adapt to get_query_result interface change. Ported from r600g commit 4445e170bee23a3607ece0e010adef7058ac6a11.
* intel: add PCI IDs for Ivy Bridge GT2 server variantEugeni Dodonov2012-04-011-0/+1
| | | | | | | Those IDs are used by Bromolow. Reviewed-by: Kenneth Graunke <[email protected]> Signed-off-by: Eugeni Dodonov <[email protected]>
* intel: Add some PCI IDs for Haswell.Kenneth Graunke2012-03-301-0/+5
| | | | | | Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eugeni Dodonov <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* r600g: add support for TN (trinity) APUsAlex Deucher2012-03-201-0/+8
| | | | | | Note: this is a candidate for the stable branches. Signed-off-by: Alex Deucher <[email protected]>
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