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* radeon: switch to 3-spaces stylePierre-Eric Pelloux-Prayer2020-03-3021-9286/+8970
| | | | | | | | For clang-format config see the previous commit. Reviewed-by: Marek Olšák <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4319> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4319>
* radeonsi: switch to 3-spaces stylePierre-Eric Pelloux-Prayer2020-03-3052-46736/+42975
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Generated automatically using clang-format and the following config: AlignAfterOpenBracket: true AlignConsecutiveMacros: true AllowAllArgumentsOnNextLine: false AllowShortCaseLabelsOnASingleLine: false AllowShortFunctionsOnASingleLine: false AlwaysBreakAfterReturnType: None BasedOnStyle: LLVM BraceWrapping: AfterControlStatement: false AfterEnum: true AfterFunction: true AfterStruct: false BeforeElse: false SplitEmptyFunction: true BinPackArguments: true BinPackParameters: true BreakBeforeBraces: Custom ColumnLimit: 100 ContinuationIndentWidth: 3 Cpp11BracedListStyle: false Cpp11BracedListStyle: true ForEachMacros: - LIST_FOR_EACH_ENTRY - LIST_FOR_EACH_ENTRY_SAFE - util_dynarray_foreach - nir_foreach_variable - nir_foreach_variable_safe - nir_foreach_register - nir_foreach_register_safe - nir_foreach_use - nir_foreach_use_safe - nir_foreach_if_use - nir_foreach_if_use_safe - nir_foreach_def - nir_foreach_def_safe - nir_foreach_phi_src - nir_foreach_phi_src_safe - nir_foreach_parallel_copy_entry - nir_foreach_instr - nir_foreach_instr_reverse - nir_foreach_instr_safe - nir_foreach_instr_reverse_safe - nir_foreach_function - nir_foreach_block - nir_foreach_block_safe - nir_foreach_block_reverse - nir_foreach_block_reverse_safe - nir_foreach_block_in_cf_node IncludeBlocks: Regroup IncludeCategories: - Regex: '<[[:alnum:].]+>' Priority: 2 - Regex: '.*' Priority: 1 IndentWidth: 3 PenaltyBreakBeforeFirstCallParameter: 1 PenaltyExcessCharacter: 100 SpaceAfterCStyleCast: false SpaceBeforeCpp11BracedList: false SpaceBeforeCtorInitializerColon: false SpacesInContainerLiterals: false Reviewed-by: Marek Olšák <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4319>
* radeon: fix includesPierre-Eric Pelloux-Prayer2020-03-304-0/+9
| | | | | | | And add required forward declarations. Reviewed-by: Marek Olšák <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4319>
* ddebug: add missing forward declarationPierre-Eric Pelloux-Prayer2020-03-301-0/+1
| | | | | Reviewed-by: Marek Olšák <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4319>
* meson: Add VS 4624 warning exclusion to remove piles of LLVM warningsDaniel Stone2020-03-301-1/+3
| | | | | | | | Reviewed-by: Jose Fonseca <[email protected]> Reviewed-by: Charmaine Lee <[email protected]> Reviewed-by: Brian Paul <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4343> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4343>
* meson: disable some more warnings on msvcErik Faye-Lund2020-03-301-1/+3
| | | | | | | | | | These warnings triggers for me, and they are harmless as-is. Let's disable them to avoid hiding actually scary warnings. Reviewed-by: Jose Fonseca <[email protected]> Reviewed-by: Charmaine Lee <[email protected]> Reviewed-by: Brian Paul <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4343>
* CI: Avoid htz4 runner for VS2019Daniel Stone2020-03-301-0/+1
| | | | | | | | | | The htz4 runner needs to be updated in order for our support binaries like Chocolatey to work. Temporarily restrict jobs to the EC2 runner until this has happened. Signed-off-by: Daniel Stone <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4371> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4371>
* intel: drop unused include directoriesEric Engestrom2020-03-2810-31/+31
| | | | | | | Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4360> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4360>
* vulkan: drop unused include directoriesEric Engestrom2020-03-283-3/+3
| | | | | | Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4360>
* meson: inline `inc_common`Eric Engestrom2020-03-2898-158/+199
| | | | | | | | | Let's make it clear what includes are being added everywhere, so that they can be cleaned up. Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4360>
* meson: use existing variables in inc_commonEric Engestrom2020-03-281-2/+1
| | | | | | | | Stepping stone to make review of the next commits easier. Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4360>
* mesa: Change _mesa_exec_malloc argument type.Vinson Lee2020-03-282-3/+3
| | | | | | | | | | | | | | | | | Fix build error. In file included from ../src/mesa/x86/rtasm/x86sse.c:7:0: ../src/mesa/main/execmem.h:31:19: error: unknown type name ‘GLuint’; did you mean ‘uint’? _mesa_exec_malloc(GLuint size); ^~~~~~ uint Suggested-by: Marek Olšák <[email protected]> Fixes: e5339fe4a47c ("Move compiler.h and imports.h/c from src/mesa/main into src/util") Signed-off-by: Vinson Lee <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4361> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4361>
* gitlab-ci: Update to current templatesMichel Dänzer2020-03-281-4/+4
| | | | | | | | | | | | | | | | | | | The .fdo.container-ifnot-exists template has been replaced by .fdo.container-build. We need to include "debian/" in FDO_REPO_SUFFIX for now, we can drop it for individual images when their tags are bumped if we want. Miscellaneous other goodies this gets us: * The templates now add some labels to images which may be useful for garbage collecting unused tags in the future. * The templates now copy the current tag from the main project registry to the forked project's if it already exists in the latter but points to a different image hash. This will avoid false failures (or passes) due to using the wrong image. Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4286> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4286>
* Revert "gitlab-ci: Disable jobs for Collabora's LAVA lab"Tomeu Vizoso2020-03-281-4/+4
| | | | | | | | | | Lab is online again. This reverts commit 1351ee03352b12690233a73e160f92da2edecf16. Signed-off-by: Tomeu Vizoso <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4347> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4347>
* radeonsi/gfx10: fix descriptors and compute registers for compute-based cullingMarek Olšák2020-03-281-14/+39
| | | | | | Acked-by: Pierre-Eric Pelloux-Prayer <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4269> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4269>
* radeonsi/gfx10: fix the wave size for compute-based cullingMarek Olšák2020-03-285-6/+19
| | | | | Acked-by: Pierre-Eric Pelloux-Prayer <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4269>
* radeonsi/gfx10: user correct ACQUIRE_MEM packet for compute-based cullingMarek Olšák2020-03-281-8/+23
| | | | | Acked-by: Pierre-Eric Pelloux-Prayer <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4269>
* radeonsi/gfx10: fix ds.ordered.add intrinsic for compute-based cullingMarek Olšák2020-03-281-0/+3
| | | | | Acked-by: Pierre-Eric Pelloux-Prayer <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4269>
* radeonsi/gfx10: don't use NGG culling if compute-based culling is usedMarek Olšák2020-03-281-0/+1
| | | | | Acked-by: Pierre-Eric Pelloux-Prayer <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4269>
* radeonsi: add num_vbos_in_user_sgprs into the shader cache keyMarek Olšák2020-03-281-0/+3
| | | | | Acked-by: Pierre-Eric Pelloux-Prayer <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4269>
* radeonsi: always create wait_mem_scratch for compute-based cullingMarek Olšák2020-03-281-1/+2
| | | | | | | used by the primitive restart emulation Acked-by: Pierre-Eric Pelloux-Prayer <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4269>
* radeonsi: set amdgpu-gds-size for mode == 2 of compute-based cullingMarek Olšák2020-03-281-1/+4
| | | | | Acked-by: Pierre-Eric Pelloux-Prayer <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4269>
* radeonsi: fix incorrect ordered_wave_id initilization for compute-based cullingMarek Olšák2020-03-281-1/+2
| | | | | Acked-by: Pierre-Eric Pelloux-Prayer <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4269>
* radeonsi: remove obsolete TODO comment related to compute-based cullingMarek Olšák2020-03-281-1/+0
| | | | | Acked-by: Pierre-Eric Pelloux-Prayer <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4269>
* lima: Implement lima_texture_subdataVasily Khoruzhick2020-03-281-13/+65
| | | | | | | | | | We can avoid intermediate copy if we implement it ourselves. Improves x11perf -shmput500 from 199.0/s to 283.0/s Reviewed-by: Erico Nunes <[email protected]> Signed-off-by: Vasily Khoruzhick <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4281> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4281>
* gitlab-ci: disable vs2019 buildRob Clark2020-03-271-1/+1
| | | | | | | | Seems to be broken atm and blocking merging anything. Signed-off-by: Rob Clark <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4272> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4272>
* freedreno/ir3/ra: re-work a6xx merged register file conflictsRob Clark2020-03-271-18/+10
| | | | | | | | | In particular setup the full/half conflicts first. This avoids spurious conflicts that where causing RA to place vecN half-regs poorly. Signed-off-by: Rob Clark <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4272> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4272>
* freedreno/ir3/ra: split building regs/classes and conflictsRob Clark2020-03-272-22/+73
| | | | | | | | | Split out the construction of registers and classes (which is the same on all gens) from setting up conflicts. Prep to re-work how we setup conflicts on a6xx+ which merged half/full register file. Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4272>
* freedreno/ir3/ra: pick higher numbered scalars in first passRob Clark2020-03-274-17/+113
| | | | | | | | | | | | | | | Since we are re-assigning the scalars anyways in the second pass, assign them to the highest free reg in the first pass (rather than lowest) to allow packing vecN regs as low as possible. Note this required some changes specifically for tex instructions with a single component writemask that is not necessarily .x, as previously these would get assigned in the first RA pass, and since they are still scalar, we'd end up w/ some r47.* and other similarly way-to-high assignments after the 2nd pass. Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4272>
* freedreno/ir3/ra: compute register target from liverangesRob Clark2020-03-272-82/+209
| | | | | | | | | | | | | Using the output of the first pass isn't ideal, as it can bake in the losses from fragmentation which the scalar pass is intended to fill in. This gets worse when we start using "vectorish" instructions, due to higher use of vecN values. Instead, we can just use the outputs of the liveness analysis to get a more accurate # of maximum live values at any point. Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4272>
* freedreno/ir3/ra: fix array liverangesRob Clark2020-03-271-1/+1
| | | | | | Fixes: 1b658533e11 ("freedreno/ir3: extend liverange of arrays") Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4272>
* freedreno/ir3/ra: add def/use iteratorsRob Clark2020-03-272-133/+202
| | | | | | | | | | | | | | Decouple the messy logic of figuring out vreg names defined/used by an instruction from the logic of what to do about it by introducing iterators. There is still *some* array vs ssa special casing in ra_block_compute_live_ranges(), but less than before. And this will avoid introducing a second copy of the def/use logic in a following patch which uses the liveranges to calculate the maximum # of live values (which is the optimal target for max physical register window to round-robin within). Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4272>
* freedreno/ir3/ra: drop extending output live-rangesRob Clark2020-03-271-7/+0
| | | | | | | | This is no longer needed as we create meta:collect instructions in the end block, which achieves the same result. Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4272>
* freedreno/ir3/ra: add helper to map name to arrayRob Clark2020-03-271-1/+24
| | | | | | | | For vreg names that refer to arrays rather than SSA values, this is the counterpart to name_to_instr(). Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4272>
* freedreno/ir3/ra: fix target register calculationRob Clark2020-03-271-1/+1
| | | | | | | | | | | Account for the # of regs an instruction writes, and fix an off-by-one. (We are about to replace this with calculating the register target using the live-ranges, but in debugging that it was useful to assert() if it chose a higher target.) Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4272>
* freedreno/ir3/ra: add helper to map name to instructionRob Clark2020-03-271-23/+36
| | | | | | | | | Extract out a helper from the select_reg callback. And include all the instructions in the hashtable, not just SFU. This will be useful in the following commits. Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4272>
* freedreno/ir3/ra: split-upRob Clark2020-03-275-352/+424
| | | | | | | | Split out regset and shared header, since the RA pass is already getting large-ish. Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4272>
* freedreno/ir3/ra: add debug option for RA debug msgsRob Clark2020-03-273-16/+37
| | | | | | | Similar to the debug switch for sched debug msgs Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4272>
* freedreno/ir3: convert debug bitfield to BITFIELD_BIT()Rob Clark2020-03-271-12/+12
| | | | | | | (Little more verbose than the kernel's BIT()) Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4272>
* freedreno/ir3: reformat disasm outputRob Clark2020-03-271-7/+17
| | | | | | | | | In particular, make sure we see all the shader-db stats. The format (order) is the sameish, except split across multiple lines to make it easier to read. Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4272>
* freedreno/ir3: fix bogus register footprint with tess/gsRob Clark2020-03-271-0/+3
| | | | | | | | When we have a tess or gs stage, VS outputs aren't normal varyings, so regid is r63.x.. we shouldn't extend our registerfootprint to 64! Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4272>
* freedreno/ir3: remove unused helperRob Clark2020-03-271-10/+0
| | | | | Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4272>
* freedreno/ir3: add bary_ij as src for meta:tex_prefetchRob Clark2020-03-271-9/+4
| | | | | | | | | | | | This way RA doesn't have to special case it in use/def accounting.. This gets rid of an extra level of split/collect, which shouldn't be needed. And interferes with scheduler trying to put tex-prefetches after inputs but before other instructions. (Otherwise it would have to figure out which split/collects need to go before the tex-prefetch) Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4272>
* freedreno/ir3: small cleanup and commentsRob Clark2020-03-2717-71/+77
| | | | | Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4272>
* freedreno/a6xx: register updateRob Clark2020-03-271-1/+3
| | | | | | | | No functional change, and this register isn't used in userspace. Just syncing from envytools tree to eliminate the delta. Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4272>
* CI: Disable Panfrost Mali-T820 jobsDaniel Stone2020-03-271-1/+1
| | | | | | | | The BayLibre T820 runners appear to be unhealthy. Signed-off-by: Daniel Stone <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4359> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4359>
* util: remove duplicated MALLOC_STRUCT and CALLOC_STRUCTMarek Olšák2020-03-271-12/+1
| | | | | | Reviewed-by: Timothy Arceri <[email protected] Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4324> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4324>
* util: don't include p_defines.h and u_pointer.h from galliumMarek Olšák2020-03-2721-26/+38
| | | | | | | It's a mess, but this is what I arrived at. Reviewed-by: Timothy Arceri <[email protected] Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4324>
* radv: stop including files from mesa/mainMarek Olšák2020-03-279-7/+14
| | | | | | Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Timothy Arceri <[email protected] Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4324>
* util: stop including files from mesa/mainMarek Olšák2020-03-275-9/+27
| | | | | Reviewed-by: Timothy Arceri <[email protected] Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4324>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-04 01:23:16 +0000