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* intel/blorp: Use nir_format_bitcast_uint_vec_unmaskedJason Ekstrand2018-05-091-41/+16
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* nir/format_convert: Add code for bitcasting vectorsJason Ekstrand2018-05-091-0/+53
| | | | | | | This is a fairly direct port from blorp. The only real change is that the nir_format_convert version doesn't assume that everything is a vec4. Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/blorp: Use ISL instead of bitcast_color_value_to_uintJason Ekstrand2018-05-091-73/+10
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/isl: Add format conversion codeJason Ekstrand2018-05-095-2/+224
| | | | | | | | | | | | | | This adds helpers to ISL to convert an isl_color_value to and from binary data encoded with a given isl_format. The conversion is done using ISL's built-in format introspection so it's fairly slow as format conversions go but it should be fine for a single pixel value. In particular, we can use this to convert clear colors. As a side-effect, we now rely on the sRGB helpers in libmesautil so we need to tweak the build system a bit. All prior uses of src/util in ISL were header-only. Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/isl/format: Get rid of the ALPHA colorspaceJason Ekstrand2018-05-092-8/+8
| | | | | | | Alpha-only formats are just linear. There's no need to specially deliminate them as being in their own colorspace. Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/isl/format: Add field locations informations to channel_layoutJason Ekstrand2018-05-092-2/+13
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/isl/format: Add a column for channel order to the tableJason Ekstrand2018-05-092-281/+282
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/blorp: Remove a pile of blorp_blit restrictionsJason Ekstrand2018-05-091-30/+33
| | | | | | | | Previously, blorp could only blit into something that was renderable. Thanks to recent additions to blorp, it can now blit into basically anything so long as it isn't compressed. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/blorp: Allow blorp blits for 16x MSAAJason Ekstrand2018-05-091-4/+0
| | | | | | | BLORP has supported 16x MSAA for quite a while now, we just never bothered to enable it for CopyTexSubImage. Reviewed-by: Topi Pohjolainen <[email protected]>
* anv: Allow blitting to/from any supported formatJason Ekstrand2018-05-092-7/+6
| | | | | | | | Now that blorp handles all the cases, why not? The only real change we have to make is to stop using anv_swizzle_for_render() in blorp_blit because it doesn't work for B4G4R4A4 and blorp now natively handles that. Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/blorp: Support the RGB workaround on more formatsJason Ekstrand2018-05-091-20/+53
| | | | | | | | Previously we only supported UINT formats because that's what blorp_copy required. If we want to use it in blorp_blit, however, we need to support everything. Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/blorp: Silently convert RGBX destination formats to RGBAJason Ekstrand2018-05-091-0/+4
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/isl: Add some helpers for working with RGBX formatsJason Ekstrand2018-05-092-0/+43
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/blorp: Handle more exotic destination formatsJason Ekstrand2018-05-092-0/+54
| | | | | | | | | | | | | | | This commit adds support for the following formats as destination formats even though the hardware does not support rendering to them: - ISL_FORMAT_R24_UNORM_X8_TYPELESS - ISL_FORMAT_A4B4G4R4_UNORM - ISL_FORMAT_L8_UNORM_SRGB - ISL_FORMAT_R9G9B9E5_SHAREDEXP This is done by using a different format and emitting shader code to fake it the rest of the way. Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/blorp: Include nir_format_convert.h in blorp_blit.cJason Ekstrand2018-05-091-19/+1
| | | | | | | nir_mask_shift_or is now defined in nir_format_convert.h so we can delete the copy in blorp_blit.c. Reviewed-by: Topi Pohjolainen <[email protected]>
* nir/format_convert: Add a function to pack RGB9_E5 formatsJason Ekstrand2018-05-091-0/+64
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* nir/format_convert: Add pack/unpack for R11F_G11F_B10FJason Ekstrand2018-05-091-0/+38
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* nir/format_convert: Add linear <-> sRGB helpersJason Ekstrand2018-05-091-0/+26
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* nir: Add the start of a format conversion helper headerJason Ekstrand2018-05-093-0/+108
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/blorp: Add swizzle support for all hardwareJason Ekstrand2018-05-092-1/+69
| | | | | | | This commit makes blorp capable of swizzling anything even on hardware that doesn't support texture swizzle. Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/isl: Add a helper for inverting swizzlesJason Ekstrand2018-05-092-0/+32
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/isl: Add a helper for composing swizzlesJason Ekstrand2018-05-092-0/+38
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* intel/isl: Add an isl_swizzle_supports_rendering helperJason Ekstrand2018-05-093-32/+71
| | | | | | | This helper encodes more details, specifically about Haswell, than the previous asserts in isl_surface_state.c. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/surface_state: Use an identity swizzle pre-HaswellJason Ekstrand2018-05-091-0/+6
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* blorp: Handle the RGB workaround more like other workaroundsJason Ekstrand2018-05-091-30/+30
| | | | | | | | | | | | | The previous version was sort-of strapped on in that it just adjusted the blit rectangle and trusted in the fact that we would use texelFetch and round to the nearest integer to ensure that the component positions matched. This new version, while slightly more complicated, is more accurate because all three components end up with exactly the same dst_pos and so they will get interpolated and sampled at the same texture coordinate. This makes the workaround suitable for using with scaled blits. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: silence unused variableLionel Landwerlin2018-05-091-1/+0
| | | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Fixes: 2dc29e095f9da ("i965: Don't leak blorp on Gen4-5.") Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]>
* intel: devinfo: silence coverity warningLionel Landwerlin2018-05-091-0/+1
| | | | | | | | It's just not possible to have a device with no subslices. CID: 1433511 Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Rafael Antognolli <[email protected]>
* dri3: Only update number of back buffers in loader_dri3_get_buffersMichel Dänzer2018-05-091-8/+11
| | | | | | | | | | | | | | And only free no longer needed back buffers there as well. We want to stick to the same back buffer throughout a frame, otherwise we can run into various issues. Bugzilla: https://bugs.freedesktop.org/105906 Bugzilla: https://bugs.freedesktop.org/106399 Fixes: 3160cb86aa92 "egl/x11: Re-allocate buffers if format is suboptimal" Reported-by: Sergii Romantsov <[email protected]> Tested-by: Eero Tamminen <[email protected]> Acked-by: Daniel Stone <[email protected]>
* anv: ignore pColorBlendState if all color attachments of the subpass are unusedSamuel Iglesias Gonsálvez2018-05-092-3/+13
| | | | | | | | | | | | | | | | | | | According to Vulkan spec: "pColorBlendState is a pointer to an instance of the VkPipelineColorBlendStateCreateInfo structure, and is ignored if the pipeline has rasterization disabled or if the subpass of the render pass the pipeline is created against does not use any color attachments." Fixes tests from CL#2505: dEQP-VK.renderpass.*.simple.color_unused_omit_blend_state v2: - Check that blend is not NULL before usage. Signed-off-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* mesa: remove hard-coded OpenGL 3.2 compat limitTimothy Arceri2018-05-091-8/+0
| | | | | | | | Just let validate_context_version() do it instead. This fixes MESA_GL_VERSION_OVERRIDE for compat, it will also allow us to enable new compat versions on a per driver bases in future. Reviewed-by: Marek Olšák <[email protected]>
* mesa: add GLSLVersionCompat constantTimothy Arceri2018-05-095-3/+10
| | | | | | | | This allows drivers to define what version of GLSL they support in compat. This will be needed in order to support compat 3.2 without breaking drivers that wont support it. Reviewed-by: Marek Olšák <[email protected]>
* mesa: dont call _mesa_override_glsl_version() in _mesa_init_constants()Timothy Arceri2018-05-091-3/+0
| | | | | | | | All drivers that support GLSL will later set their default GLSL versions overriding this override call. They currently all call _mesa_override_glsl_version() again later in order to support overrides. Reviewed-by: Marek Olšák <[email protected]>
* mesa: dont set GLSLVersion in _mesa_init_constants()Timothy Arceri2018-05-091-1/+0
| | | | | | | Just leave it as 0 and let the drivers set it (as they already do) to avoid redundantly initialising it. Reviewed-by: Marek Olšák <[email protected]>
* pipe-loader: Free driver_name in error pathJan Vesely2018-05-081-0/+1
| | | | | | CC: <[email protected]> Signed-off-by: Jan Vesely <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* glsl: change ast_type_qualifier bitset size to work around GCC 5.4 bugBrian Paul2018-05-081-1/+7
| | | | | | | | | | | | | | | Change the size of the bitset from 128 bits to 96. This works around an apparent GCC 5.4 bug in which bad SSE code is generated, leading to a crash in ast_type_qualifier::validate_in_qualifier() (ast_type.cpp:654). This can be repro'd with the Piglit test tests/spec/glsl-1.50/execution/ varying-struct-basic-gs-fs.shader_test Bugzilla:https://bugs.freedesktop.org/show_bug.cgi?id=105497 Cc: [email protected] Reviewed-by: Charmaine Lee <[email protected]> Tested-by: Charmaine Lee <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965: Dump validation list on INTEL_DEBUG=bat,submit.Kenneth Graunke2018-05-081-1/+3
| | | | | | | | | | This is really useful when debugging any sort of buffer management issues, so just printing it during INTEL_DEBUG=bat,submit seems reasonable. With bat, we're already spamming so much output that it doesn't really hurt. With submit, it's still easy to grep for the older information, and the new information is nice too. Reviewed-by: Scott D Phillips <[email protected]>
* i965/miptree: Remove redundant fields from intel_miptree_aux_bufferJason Ekstrand2018-05-082-37/+7
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Simplify brw_emit_depthbuffer and brw_emit_depth_stencil_hizJason Ekstrand2018-05-081-81/+26
| | | | | | | | Now that we're using ISL, a good chunk of brw_emit_depthstencil is pointless checks which ISL will do for us anyway. Since we only have one manual depth buffer emit function, move the useful bits into it. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Move brw_emit_depth_stencil_hiz higher up in the fileJason Ekstrand2018-05-081-50/+40
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Use ISL for emitting depth/stencil/hiz state on gen6+Jason Ekstrand2018-05-089-671/+129
| | | | | | | | | | | | | | We leave gen4-5 alone because the ISL code hasn't really been well- tested on gen4-5 or with combined depth-stencil because we don't use BLORP for depth operations on gen4-5. Also, the gen4-5 code has to deal with intratile offsets for LOD hacks and ISL doesn't handle those yet. We could make ISL handle gen4-5 capable or we could just not bother. Among other things, this should make future platform enabling easier because it means we don't have to update multiple (or hand-rolled!) depth stencil emit paths. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Use the brw_depthbuffer atom on all gensJason Ekstrand2018-05-084-17/+4
| | | | | | | | | | The only reason why we had two atoms was that the one we used for gen7+ depended on _NEW_DEPTH and _NEW_STENCIL as well as _NEW_BUFFERS. Since this is no longer true, we can combine them into one atom. We do add a dependence on BRW_NEW_AUX_STATE but that should never get set on gen4-5 so adding it is a no-op for those platforms. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Always set depth/stencil write enables on gen7+Jason Ekstrand2018-05-082-11/+6
| | | | | | | | | The hardware will AND these fields with the corresponding fields in DEPTH_STENCIL_STATE so there's no real reason to toggle them on and off based on state bits. This removes our reliance on the _NEW_DEPTH and _NEW_STENCIL state bits and better matches what ISL does. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Re-order depth/stencil/hiz/clear packets to match ISLJason Ekstrand2018-05-083-47/+47
| | | | | Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Re-emit depth/stencil/hiz on BRW_NEW_AUX_STATEJason Ekstrand2018-05-081-1/+2
| | | | | | | | | | Certain things can change the aux usage or fast clear color of a depth surface and we want to re-emit if that happens. For instance, if you do a fast depth clear of an already clear depth surface, we will just set the clear color and not do anything else. In that case, we could fail to re-emit 3DSTATE_CLEAR_PARAMS and not get the new fast-clear color. Reviewed-by: Kenneth Graunke <[email protected]>
* intel: devinfo: fix assertion on devices with odd number of EUsLionel Landwerlin2018-05-081-5/+1
| | | | | | | | | | | | I forgot to change the assert in the second helper function in a previous change. This hit the assert() on a Broadwell platform with 1 slice, 3 subslices but all EUs disabled in subslice 1 & 2. Fixes: c1900f5b0fb ("intel: devinfo: add helper functions to fill fusing masks values") Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* vulkan/wsi: Only use LINEAR modifier for prime if supported.Bas Nieuwenhuizen2018-05-083-2/+5
| | | | | | | | | | | | This was setting the LINEAR modifier if neither the X server nor the driver supported modifiers. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106180 Fixes: c80c08e226 "vulkan/wsi/x11: Add support for DRI3 v1.2" CC: 18.1 <[email protected]> Tested-by: Abel Garcia Dorta <[email protected]> Acked-by: Daniel Stone <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* eg/compute: Drop reference to kernel_param bo in destructorJan Vesely2018-05-081-0/+1
| | | | | | CC: <[email protected]> Signed-off-by: Jan Vesely <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* r600: Cleanup constant buffers on context destructionJan Vesely2018-05-081-1/+5
| | | | | | CC: <[email protected]> Signed-off-by: Jan Vesely <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* mesa/formatquery: remove online compression check on is_resource_supportedAlejandro Piñeiro2018-05-081-2/+1
| | | | | | | | | | | | | | | is_resource_supported returns if the combination of target/internalformat is supported in at least one operation. Online compression is only mandatory for glTexImage2D. Some formats doesn't support online compression, but can be used in any case, with glCompressed*D methods. Without this commit, ETC2 internalformats were returning FALSE, even for the drivers supporting it. So any other query (like TEXTURE_COMPRESSED) was returning FALSE/NONE instead of the proper value. Reviewed-by: Marek Olšák <[email protected]>
* intel/genxml: Assert that genxml field start and ends are sane.Kenneth Graunke2018-05-071-0/+7
| | | | | | | | | Chris recently fixed a bunch of genxml end < start bugs, as well as booleans that are wider than a bit. These are way too easy to write, so asserting that the fields are sane is a good plan. Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]> Acked-by: Jason Ekstrand <[email protected]>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-13 19:09:44 +0000