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* spirv: Add better validation to Op[Spec]ConstantJason Ekstrand2018-01-081-2/+7
| | | | Reviewed-by: Lionel Landwerlin <[email protected]>
* spirv: Remove a pointless assignment in SpvOpSpecConstantJason Ekstrand2018-01-081-1/+0
| | | | | | We re-assign later inside the bit_size switch Reviewed-by: Lionel Landwerlin <[email protected]>
* spirv: Unify boolean constants and add better validationJason Ekstrand2018-01-081-10/+11
| | | | Reviewed-by: Lionel Landwerlin <[email protected]>
* spirv/info: Add spirv_op_to_stringJason Ekstrand2018-01-082-0/+11
| | | | Reviewed-by: Lionel Landwerlin <[email protected]>
* spirv: Make 'info' a local array spirv_info_c.pyJason Ekstrand2018-01-081-3/+5
| | | | Reviewed-by: Lionel Landwerlin <[email protected]>
* spirv: Add better error messages in vtn_value helpersJason Ekstrand2018-01-081-11/+15
| | | | Reviewed-by: Lionel Landwerlin <[email protected]>
* spirv: Import 1.2 rev 3 headers and grammar from KhronosCaio Marcelo de Oliveira Filho2018-01-082-164/+431
| | | | Reviewed-by: Jason Ekstrand <[email protected]>
* radv: get InstanceID from VGPR1 (or VGPR2 for tess) instead of VGPR3Samuel Pitoiset2018-01-081-8/+24
| | | | | | | | | VGPR1 = InstanceID / StepRate0; // StepRate0 can be set to 1 Ported from RadeonSI. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: avoid PS partial flushes when viewports/scissors don't changeSamuel Pitoiset2018-01-081-6/+33
| | | | | | | | | | | | | For Vega10 and Raven that need a special workaround for the scissor bug. This seems to give a minor boost for Talos and Dota 2, at least. To reduce the cost of memcmp, the driver checks if it's really useful to do the comparison. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: add has_scissor_bug for Vega10 and RavenSamuel Pitoiset2018-01-083-2/+6
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv/gfx9: do not load VGPR1 when GS uses points or linesSamuel Pitoiset2018-01-081-1/+3
| | | | | | | | VGPR1 is only needed for topology that needs 3 offsets like triangles or quads. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: make shader BOs read-only for the GPUSamuel Pitoiset2018-01-083-1/+7
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: make descriptor BOs read-only for the GPUSamuel Pitoiset2018-01-082-3/+7
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: make the indirect GFX config BO read-only for the GPUSamuel Pitoiset2018-01-081-1/+2
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv/winsys: make IBs read-only for the GPUSamuel Pitoiset2018-01-081-6/+11
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv/winsys: add RADEON_FLAG_READ_ONLYSamuel Pitoiset2018-01-082-1/+4
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv/winsys: rework radv_amdgpu_bo_va_op()Samuel Pitoiset2018-01-081-17/+23
| | | | | | | Needed for the following commit. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* link mesautil with pthreadsIgor Gnatenko2018-01-081-0/+2
| | | | | | | | | | | | | | | | | | | | | | ../../src/util/.libs/libmesautil.a(libmesautil_la-u_queue.o): In function `u_thread_setname': /builddir/build/BUILD/mesa-17.3.1/src/util/../../src/util/u_thread.h:66: undefined reference to `pthread_setname_np' ../../src/util/.libs/libmesautil.a(libmesautil_la-u_queue.o): In function `thrd_join': /builddir/build/BUILD/mesa-17.3.1/src/util/../../include/c11/threads_posix.h:336: undefined reference to `pthread_join' ../../src/util/.libs/libmesautil.a(libmesautil_la-u_queue.o): In function `u_thread_create': /builddir/build/BUILD/mesa-17.3.1/src/util/../../src/util/u_thread.h:48: undefined reference to `pthread_sigmask' ../../src/util/.libs/libmesautil.a(libmesautil_la-u_queue.o): In function `thrd_create': /builddir/build/BUILD/mesa-17.3.1/src/util/../../include/c11/threads_posix.h:296: undefined reference to `pthread_create' ../../src/util/.libs/libmesautil.a(libmesautil_la-u_queue.o): In function `u_thread_create': /builddir/build/BUILD/mesa-17.3.1/src/util/../../src/util/u_thread.h:50: undefined reference to `pthread_sigmask' /builddir/build/BUILD/mesa-17.3.1/src/util/../../src/util/u_thread.h:50: undefined reference to `pthread_sigmask' ../../src/util/.libs/libmesautil.a(libmesautil_la-u_queue.o): In function `call_once': /builddir/build/BUILD/mesa-17.3.1/src/util/../../include/c11/threads_posix.h:96: undefined reference to `pthread_once' ../../src/util/.libs/libmesautil.a(libmesautil_la-u_queue.o): In function `u_thread_get_time_nano': /builddir/build/BUILD/mesa-17.3.1/src/util/../../src/util/u_thread.h:84: undefined reference to `pthread_getcpuclockid' collect2: error: ld returned 1 exit status Reviewed-by: Adam Jackson <[email protected]> Signed-off-by: Igor Gnatenko <[email protected]>
* anv: Allow PMA optimization to be enabled in secondary command buffersAlex Smith2018-01-081-1/+21
| | | | | | | | | | | | | | | | | This was never enabled in secondary buffers because hiz_enabled was never set to true for those. If the app provides a framebuffer in the inheritance info when beginning a secondary buffer, we can determine if HiZ is enabled and therefore allow the PMA optimization to be enabled within the command buffer. This improves performance by ~13% on an internal benchmark on Skylake. v2: Use anv_cmd_buffer_get_depth_stencil_view(). Signed-off-by: Alex Smith <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* glsl: Respect std430 layout in lower_buffer_accessFlorian Will2018-01-081-4/+10
| | | | | | | | | | | Respect the std430 rules for determining offset and size of struct members when using a std430 buffer. std140 rules lead to wrong buffer offsets in that case. Fixes my test case attached in Bugzilla. No piglit changes. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104492 Reviewed-by: Timothy Arceri <[email protected]>
* nir: fix st_nir_assign_var_locations for patch variablesKarol Herbst2018-01-081-2/+6
| | | | | | Signed-off-by: Karol Herbst <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* nvc0: enable bindless on keplerIlia Mirkin2018-01-073-4/+5
| | | | | | | All the functionality is in. Maxwell will take a little bit more enablement work. Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0: add bindless image support for keplerIlia Mirkin2018-01-0711-75/+272
| | | | | | | | A part of the driver constbuf area is allocated for bindless images. Any update requires uploading to all driver constbufs. This also extends the driver constbuf to 64KB, up from 2KB. Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0: add support for bindless textures on kepler+Ilia Mirkin2018-01-0710-5/+183
| | | | | | | | | This keeps a list of resident textures (per context), and dumps that list into the active buffer list when submitting. We also treat bindless texture fetches slightly differently, wrt the meaning of indirect, and not requiring the SAMPLER file to be used. Signed-off-by: Ilia Mirkin <[email protected]>
* nv50/ir: use the image info in the instruction rather than declIlia Mirkin2018-01-071-52/+24
| | | | | | | | | | In preparation for bindless images, we have to retrieve the target/format info from the instruction directly, as there will be no declaration. Furthermore, for bound images, this information is still available in the instruction, so we can drop the declaration-based mechanism entirely. Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0/ir: safen up lowering logic against overwriting reused valuesIlia Mirkin2018-01-071-2/+4
| | | | | | | | | I'm fairly sure both of the changed sites are OK as-is, but they're fragile, so this is just safening them up. Since this is happening pre-ssa, we don't want to be overwriting values that may potentially get used later on. Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0: update tic in-place when buffer address changesIlia Mirkin2018-01-072-14/+21
| | | | | | This is helpful for bindless, where changing TIC id's is undesirable. Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0: ensure that pushbuf keeps ref to old text/tls bosIlia Mirkin2018-01-071-0/+13
| | | | | | | | | If we free the bo, then the PTE may get deallocated immediately. We have to make sure that the submission includes a ref to the old bo so that it remains mapped for the duration of the command execution. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* i965: Torch public intel_batchbuffer_emit_dword/float helpers.Kenneth Graunke2018-01-062-15/+2
| | | | | | | | | | | intel_batchbuffer_emit_float is dead code, it should go. intel_batchbuffer_emit_dword only had one user, which had bungled using them by forgetting to call intel_batchbuffer_require_space first. So it seems wise to delete these unsafe helpers. Cc: [email protected] Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Require space for MI_BATCHBUFFER_END.Kenneth Graunke2018-01-061-2/+5
| | | | | | | | | | | intel_batchbuffer_emit_dword doesn't reserve space for the DWord it emits. In the past, we had some reserved batch space to ensure this worked. With the switch to growing batches, we need to actually request space so that we grow if necessary. Fixes: 2c46a67b4138631217141f (i965: Delete BATCH_RESERVED handling.) Cc: [email protected] Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Shut up a few unused variable warnings.Kenneth Graunke2018-01-061-2/+2
| | | | | If asserts are disabled, you get pointless warnings about devinfo being used (it's used to assert on devinfo->gen).
* ac: add ac_build_fmin/fmax helpersMarek Olšák2018-01-062-15/+22
| | | | Reviewed-by: Samuel Pitoiset <[email protected]>
* mesa: remove dd_function_table::GetCompressedTexSubImage and clean it upMarek Olšák2018-01-065-32/+11
| | | | Reviewed-by: Ian Romanick <[email protected]>
* mesa: Tidy up the 4.6 section of GL4x.xmlNeil Roberts2018-01-061-5/+10
| | | | | | | | The enums are moved to the top and indented like the rest of the file. Comments are added to split up the function aliases by corresponding extension. This should make no functional difference. Reviewed-by: Ian Romanick <[email protected]>
* radv: remove unused radv_color_buffer_info::cb_clear_valueXSamuel Pitoiset2018-01-051-2/+0
| | | | | | | Found by inspection. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas nieuwenhuizen <[email protected]>
* anv: Take write mask into account in has_color_buffer_write_enabledAlex Smith2018-01-051-9/+18
| | | | | | | | | | | | | | | | | | | | If we have a color attachment, but its writes are masked, this would have still returned true. This is inconsistent with how HasWriteableRT in 3DSTATE_PS_BLEND is set, which does take the mask into account. This could lead to PixelShaderHasUAV not being set in 3DSTATE_PS_EXTRA if the fragment shader does use UAVs, meaning the fragment shader may not be invoked because HasWriteableRT is false. Specifically, this was seen to occur when the shader also enables early fragment tests: the fragment shader was not invoked despite passing depth/stencil. Fix by taking the color write mask into account in this function. This is consistent with how things are done on i965. Signed-off-by: Alex Smith <[email protected]> Cc: [email protected] Reviewed-by: Iago Toral Quiroga <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* mesa: Add GL4.6 aliases of functions from GL_ARB_indirect_parametersNeil Roberts2018-01-051-0/+22
| | | | Reviewed-by: Ian Romanick <[email protected]>
* radv: enable denorms for 64-bit and 16-bit floatsSamuel Pitoiset2018-01-051-0/+14
| | | | | | | | | | | Similar to RadeonSI. This fixes: dEQP-VK.image.texel_view_compatible.graphic.basic.attachment_read.bc*r16g16b16a16_sfloat dEQP-VK.image.extended_usage_bit.attachment_write.r16_sfloat Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* amd/common: correctly detect if we need ring buffersSamuel Pitoiset2018-01-051-7/+9
| | | | | | | | | | | | When allocate_user_sgprs() was called, ctx->stage was actually unset and 0 is for the vertex shader. This doesn't change anything for now because of the spill support thing. Though, the number of user SGPRs has to be fixed for merged shaders on GFX9. It was broken before anyway. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* amd/common: use ac_image_load when lod is zeroSamuel Pitoiset2018-01-051-1/+3
| | | | | | | | | This might decrease VGPR spilling, because we no longer have to use v4i32 for 2D fetches when level == 0. We now use v2i32 for those cases. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radv: limit the scissor bug workaround to Vega 10 and RavenSamuel Pitoiset2018-01-051-1/+6
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* glsl/standalone: set MaxTransformFeedbackBuffersAlejandro Piñeiro2018-01-051-0/+3
| | | | | | | | Using 4, as it is the default value on mesa. See mesa/main/config.h and the following commit that introduced the value: 15ac66e331abdab12e882d80a6b4f647bc905298 Reviewed-by: Ian Romanick <[email protected]>
* glsl/standalone: set MaxVertexStreamsAlejandro Piñeiro2018-01-051-0/+3
| | | | | | | ARB_transform_feedback3 sets a minimum of 1, ARB_gpu_shader5 a minimum of 4. It shouldn't matter too much, so choosing the later. Reviewed-by: Ian Romanick <[email protected]>
* glsl/standalone: set MaxUniformBufferBindingsAlejandro Piñeiro2018-01-051-0/+3
| | | | | | | | Used to handle how many ubo you can define on the context. Minimimum defined as 36 on ARB_uniform_buffer_object spec, up to 84 on OpenGL 4.6 (12 per stage at each moment). Reviewed-by: Ian Romanick <[email protected]>
* glsl/standalone: point which arguments are mandatoryAlejandro Piñeiro2018-01-051-1/+4
| | | | | | | Every now and then I execute the standalone compiler, get the non-version error, and need to remember what I'm doing wrong Reviewed-by: Ian Romanick <[email protected]>
* ac: rework ac_llvm_extract_elem()Timothy Arceri2018-01-051-3/+3
| | | | | | | Simplifies the logic a little and asserts index is 0. Suggested-by: Nicolai Hähnle <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* st/glsl_to_nir/radeonsi: enable tessellation shadersTimothy Arceri2018-01-052-1/+5
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* gallium/tgsi: add patch support to tgsi_get_gl_varying_semantic()Timothy Arceri2018-01-051-3/+8
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: add dummy implementation of si_nir_scan_tess_ctrl()Timothy Arceri2018-01-053-0/+23
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* ac/radeonsi: add load_tess_coord() to the abiTimothy Arceri2018-01-053-24/+42
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
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