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* freedreno: flush immediately when reading a pending batchRob Clark2018-07-172-30/+32
* freedreno: get rid of noop renderRob Clark2018-07-174-21/+6
* freedreno: fix samples=0 vs samples=1 confusionRob Clark2018-07-171-1/+1
* freedreno: comment for _invalidate_batch()Rob Clark2018-07-171-3/+13
* freedreno: hold batch references when flushingRob Clark2018-07-171-32/+38
* nir/spirv: print id for unsupported alu opcodeKarol Herbst2018-07-171-1/+1
* nir: prepare for bumping up max components to 16Karol Herbst2018-07-1713-53/+57
* radv/winsys: use alloca() for semaphore dependenciesSamuel Pitoiset2018-07-171-6/+2
* radv: reduce number of CB/DB meta flushes for VK_ACCESS_TRANSFER_WRITE_BITSamuel Pitoiset2018-07-171-6/+14
* radv: fix implementation of VK_KHR_create_renderpass2 for multiviewsSamuel Pitoiset2018-07-171-12/+1
* virgl: respect max_vertex_attrib_stride capErik Faye-Lund2018-07-173-2/+5
* virgl: Fix flush in virgl_encoder_inline_write.Lepton Wu2018-07-171-1/+1
* virgl: implement set_min_samplesErik Faye-Lund2018-07-175-0/+28
* glsl: do second pass of const propagation in loopsCaio Marcelo de Oliveira Filho2018-07-161-6/+23
* glsl: don't let an 'if' then-branch kill const propagation for else-branchCaio Marcelo de Oliveira Filho2018-07-161-16/+23
* v3d: Disable shader-db cycle estimates until we sort out TMU estimates.Eric Anholt2018-07-161-1/+4
* v3d: Emit the lowered uniform just before its first use in a block.Eric Anholt2018-07-161-20/+18
* v3d: Add an assert that we don't provide an invalid texture return words.Eric Anholt2018-07-161-0/+8
* v3d: Apply GFXH-1625 restriction on TMUWT in the end of the shader.Eric Anholt2018-07-161-0/+4
* intel/batch_decoder: decoding of 3DSTATE_CONSTANT_BODY.Sergii Romantsov2018-07-162-30/+20
* r600: fix build after the removal of RADEON_PRIO_* flagsMarek Olšák2018-07-167-21/+12
* nir: fix msvc buildRoland Scheidegger2018-07-161-1/+1
* nir/worklist: Rework the foreach macroJason Ekstrand2018-07-162-4/+3
* intel: tools: Fix uninitialized variable warnings in intel_dump_gpu.Eric Anholt2018-07-161-0/+2
* spirv: Fix a couple of image atomic load/store bugsJason Ekstrand2018-07-161-17/+30
* winsys/amdgpu: clean up error handling in amdgpu_cs_submit_ibMarek Olšák2018-07-161-9/+8
* radeonsi: rework RADEON_PRIO flags to be <= 31Marek Olšák2018-07-166-29/+30
* radeonsi: merge DCC/CMASK/HTILE priority flagsMarek Olšák2018-07-166-12/+8
* radeonsi: remove non-GFX BO priority flagsMarek Olšák2018-07-168-19/+7
* winsys/amdgpu: use alloca when using global_bo_listMarek Olšák2018-07-161-9/+1
* winsys/amdgpu: remove label bo_list_errorMarek Olšák2018-07-161-12/+16
* winsys/amdgpu: always update gfx_bo_list_counterMarek Olšák2018-07-161-3/+3
* winsys/amdgpu: make amdgpu_cs_context::flags & handles localMarek Olšák2018-07-162-22/+5
* mesa/virgl: Fix off-by-one and copy-paste error in multisample position evalu...Gert Wollny2018-07-161-3/+3
* nouveau: fix 3D blitter for unsigned to signed integer conversionsKarol Herbst2018-07-152-10/+22
* nir: fix printing of vec16 typeKarol Herbst2018-07-151-0/+1
* nir/spirv: implement BuiltInWorkDimRob Clark2018-07-155-0/+9
* nir/spirv: print id for unsupported builtinsKarol Herbst2018-07-151-1/+1
* intel/blorp: Handle 3-component formats in clearsJason Ekstrand2018-07-133-11/+92
* intel/blorp: Fix blits to R8G8B8_UNORM_SRGBJason Ekstrand2018-07-131-0/+4
* util/hash_table: add helper to remove entry by keyCaio Marcelo de Oliveira Filho2018-07-136-1/+78
* nir/lower_tex: Use nir_format_srgb_to_linearJason Ekstrand2018-07-131-18/+3
* vc4: Tell NIR to lower fdiv instructionsJason Ekstrand2018-07-131-0/+1
* docs: Update news, calendar, and relnotes for 18.1.4Dylan Baker2018-07-133-7/+8
* docs: Add sha256 sums for 18.1.4 tarballsDylan Baker2018-07-131-2/+2
* docs: Add release notes for 18.1.4Dylan Baker2018-07-131-0/+150
* vc4: Switch to using u_transfer_helper for MSAA maps.Eric Anholt2018-07-132-100/+16
* v3d: Work around GFXH-1461 bug losing our Z/S clears.Eric Anholt2018-07-131-0/+30
* meson: Move xvmc test tools from unit tests to installed tools.Eric Anholt2018-07-133-19/+15
* r600: Add spill output to group only if register or target index changesGert Wollny2018-07-131-24/+45
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