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* intel: Refactor code in intel_miptree_choose_tiling().Kenneth Graunke2013-04-101-4/+6
| | | | | | | | | This reduces the nesting level slightly, and in my opinion, makes it a bit easier to follow. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Chad Versace <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* intel: Move the max_gtt_map_object_size estimation to intel_context.Kenneth Graunke2013-04-103-18/+20
| | | | | | | | We need know this in order to decide what tiling mode to use. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Chad Versace <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* r600g: Add support for GL_ARB_texture_buffer_rangeFredrik Höglund2013-04-113-5/+11
| | | | Reviewed-by: Marek Olšák <[email protected]>
* i965/blorp: Remove unnecessary test in gen7_blorp_emit_depth_stencil_config.Paul Berry2013-04-101-7/+5
| | | | | | | | | | | gen7_blorp_emit_depth_stencil_config() is only called when params->depth.mt is non-null. Therefore, it's not necessary to do an "if (params->depth.mt)" test inside it. The presence of this if test was misleading static analysis tools (and briefly, me) into thinking that gen7_blorp_emit_depth_stencil_config() might sometimes access uninitialized data and dereference a null pointer. Reviewed-by: Kenneth Graunke <[email protected]>
* r600g: fix valgrind warning on CaymanMarek Olšák2013-04-101-1/+1
| | | | Warning: "Conditional jump or move depends on uninitialised value(s)".
* gallivm/tgsi: handle untyped movesZack Rusin2013-04-102-0/+10
| | | | | | | | | | | both mov and ucmp can be used to move variables of any type. correctly note that about ucmp in the tgsi_info and make sure gallivm can handle that by correctly casting the untyped moves. Signed-off-by: Zack Rusin <[email protected]> Reviewed-by: Jose Fonseca <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* gallivm: fix loops and conditionals within GSZack Rusin2013-04-102-19/+105
| | | | | | | | | | | | | We were using simple temporaries, without using alloca or phi nodes which meant that on every iteration of the loop our temporaries, which were holding the number of vertices and primitives which were emitted, were being reset to zero. Now we're using alloca to allocate those variables to preserve them across conditionals. Signed-off-by: Zack Rusin <[email protected]> Reviewed-by: Jose Fonseca <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* llvmpipe: implement PIPE_QUERY_SO_STATISTICSZack Rusin2013-04-102-0/+21
| | | | | | | | | | We were missing the implementation of PIPE_QUERY_SO_STATISTICS query, this change implements it on top of the existing facilities. Signed-off-by: Zack Rusin <[email protected]> Reviewed-by: Jose Fonseca <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* gallivm: fix unsigned divide and remainder opcodesZack Rusin2013-04-101-4/+33
| | | | | | | | | | We want to both make sure we never divide by zero to not generate sigfpe and that divide by zero is guaranteed to return 0xffffffff. Based on José idea. Signed-off-by: Zack Rusin <[email protected]> Reviewed-by: Jose Fonseca <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* gallivm: fix breakcZack Rusin2013-04-101-12/+14
| | | | | | | | | we break when the mask values are 0 not, 1, plus it's bit comparison not a floating point comparison. This fixes both. Signed-off-by: Zack Rusin <[email protected]> Reviewed-by: Jose Fonseca <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* intel/hsw: Enable hiz (v2)Chad Versace2013-04-102-2/+51
| | | | | | | | | | | | | | | | | | | Enable hiz by setting intel_context::has_hiz. However, to work around a hardware bug, we selectively enable hiz for only nicely aligned miptree slices. No Piglit regressions on Haswell 0x0d26 rev07 when based atop mesa-master-4ad3601. Improves the performance of GLB27_TRex_C24Z16_FixedTimeStep by 18.52% (hsw-0x0d26-rev07; kernel-3.9.0-rc1; GLBenchmark 2.7.0 Release a68901; samples=3). v2: Replace the check for IS_HASWELL(devid) in intel_miptree_slice_has_hiz() with a conditional set of has_hiz. [for anholt] Reviewed-by: Eric Anholt <[email protected]> Signed-off-by: Chad Versace <[email protected]>
* i965: Remove brw_context::depthstencil::hiz_mtChad Versace2013-04-102-3/+0
| | | | | | | | After recent refactorings, the field is written but no longer read. Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Signed-off-by: Chad Versace <[email protected]>
* intel: Replace checks for hiz_mt with intel_has*hiz()Chad Versace2013-04-108-40/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | When appropriate, replace each check `hiz_mt != NULL` with either a call to intel_miptree_slice_has_hiz() or intel_renderbuffer_has_hiz(). No behavioral change. This prepares for selectively enabling hiz on individual miptree slices for Haswell. This refactoring had several side effects. 1. To prevent new warnings about discarding the const qualifier, I removed 'const' from some variable declarations in intel_validate_framebuffer(). The alternative was to add const qualifiers to multiple function signatures in the intel_renderbuffer_has_hiz call graph. Since the dominant convention in the Intel code is to not qualify function parameters as const, I chose to remove rather than add const qualifiers. 2. I changed the signature of brw_emit_depth_stencil_hiz() by replacing `struct intel_mipmap_tree *hiz_mt` with `bool hiz`. The function used hiz_mt mostly as a boolean indicator of the presence of hiz, so the signature change is consistent with the patch's goal. Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Signed-off-by: Chad Versace <[email protected]>
* i965: Change signature of brw_get_depthstencil_tile_masks()Chad Versace2013-04-104-3/+16
| | | | | | | | | | Add new parameters `depth_level` and `depth_layer`, which specify depth miptree's slice of interest. A following patch will pass the new parameters through to intel_miptree_slice_has_hiz(). Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Signed-off-by: Chad Versace <[email protected]>
* i965/blorp: Add fields brw_blorp_mip_info::level,layerChad Versace2013-04-102-0/+15
| | | | | | | | | The new fields define the 2D miptree slice to be used. A following patch will pass the new fields through to intel_miptree_slice_has_hiz(). Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Signed-off-by: Chad Versace <[email protected]>
* intel: Add field intel_mipmap_slice::has_hizChad Versace2013-04-104-2/+44
| | | | | | | | | | | | | | | | | On Haswell, HiZ will selectively be enabled on individual miptree slices to workaround a hardware bug. The new field 'has_hiz' indicates if HiZ is enabled for a given slice. Also add two new accessor functions for this field. intel_miptree_slice_has_hiz intel_renderbuffer_has_hiz The new field and accessor functions are not yet used. Also, this patch introduces no behavioral change because, in this patch, intel_miptree_alloc_hiz() sets has_hiz for all slices. Reviewed-by: Eric Anholt <[email protected]> Signed-off-by: Chad Versace <[email protected]>
* i965/blorp: Align rectangle primitive for hiz opsChad Versace2013-04-101-0/+29
| | | | | | | | | | The hardware docs and the simulator require that the rectangle primitive emitted during fast depth clears and hiz resolves must be aligned to 8x4 pixels. Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Signed-off-by: Chad Versace <[email protected]>
* i965/vs: Use GRFs for pull constant offsets on gen7.Eric Anholt2013-04-106-22/+56
| | | | | | | | | | | | | This allows the computation of the offset to get written directly into the message source. shader-db results: total instructions in shared programs: 3308390 -> 3283025 (-0.77%) instructions in affected programs: 442998 -> 417633 (-5.73%) No difference in GLB2.7 low res (n=9). Reviewed-by: Matt Turner <[email protected]>
* i965/vs: When asked to make a dst_reg for a src.xxxx, just write to src.x.Eric Anholt2013-04-101-1/+8
| | | | | | | | | | | | | We have several places in our pull constant handling where we make a temporary src_reg for an int, and then turn it into a dst. In doing so, we were writing to the dst.xyzw, so we never register coalesced it with a later mov from dst.x to real_dst.x. These extra channels written would be removed if we had channel-wise DCE in the backend, but we don't. Fix it for now by just not writing these extra channels that won't get used. Reviewed-by: Matt Turner <[email protected]>
* i965/gen6: Reduce updates of transform feedback offsets with HW contexts.Eric Anholt2013-04-101-1/+1
| | | | | | | | | | | | The software-tracked transform feedback offsets (svbi_0_starting_index) are incorrect in the presence of primitive restart, so we were actually updating it with a bogus value if the batch wrapped and we emitted the packet again during a single transform feedback. By reducing state emission, we avoid the bug. Fixes piglit OpenGL 3.1/primitive-restart-xfb flush Reviewed-by: Paul Berry <[email protected]> NOTE: This is a candidate for the 9.1 branch.
* i965/gen7: Skip resetting SOL offsets at batch start with HW contexts.Eric Anholt2013-04-102-6/+21
| | | | | | | | | | | | The software-tracked transform feedback offsets (svbi_0_starting_index) are incorrect in the presence of primitive restart, so we can't reliably compute offsets for our buffer pointers after a batch flush. Thanks to HW contexts, our transform feedback offsets are now saved, so we can just keep using the ones from before the batch wrap. Fixes piglit OpenGL 3.1/primitive-restart-xfb flush Reviewed-by: Paul Berry <[email protected]> NOTE: This is a candidate for the 9.1 branch.
* radeonsi: remove sampler writemask v3Christian König2013-04-102-13/+8
| | | | | | | | v2: fix instrinsic name as well v3: LLVM revision incremented as well Signed-off-by: Christian König <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* pipe-loader: Fix out of source buildNiels Ole Salscheider2013-04-101-2/+2
| | | | Signed-off-by: Niels Ole Salscheider <[email protected]>
* st/mesa: remove #if FEATURE_GL/ES testsBrian Paul2013-04-091-7/+0
| | | | Reviewed-by: Jordan Justen <[email protected]>
* mesa: remove old comment about FEATURE_GLBrian Paul2013-04-091-2/+1
| | | | Reviewed-by: Jordan Justen <[email protected]>
* mesa: remove #ifdef FEATURE_ES2, add some comments insteadBrian Paul2013-04-091-2/+9
| | | | Reviewed-by: Jordan Justen <[email protected]>
* st/mesa: remove #include mfeatures.hBrian Paul2013-04-0924-24/+0
| | | | | | None of these were needed. Reviewed-by: Jordan Justen <[email protected]>
* docs: initial 9.2 release notes fileBrian Paul2013-04-092-0/+66
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* st/osmesa: re-use buffers in OSMesaMakeCurrent()Brian Paul2013-04-091-7/+54
| | | | | | | Rather than creating a new buffer each time. Fixes problems found with vtk. Tested-by: Kevin H. Hobbs <[email protected]>
* mesa: update derived framebuffer state in GetMultisamplefvMarek Olšák2013-04-101-0/+5
| | | | | | This makes sure that ctx->DrawBuffer->Visual.samples is up-to-date. Reviewed-by: Eric Anholt <[email protected]>
* mesa: fix glGet queries depending on derived framebuffer state (v2)Marek Olšák2013-04-102-7/+26
| | | | | | | | | | | | | "ctx->DrawBuffer->Visual" might be invalid if (NewState &_NEW_BUFFERS) != 0. v2: also fix: - RGBA_INTEGER_MODE_EXT - RGBA_FLOAT_MODE_ARB (also check API support) - FRAMEBUFFER_SRGB_CAPABLE_EXT NOTE: This is a candidate for stable branches. Reviewed-by: Eric Anholt <[email protected]>
* i965/gen7.5: Allow HW primitive restart for all primitive types.Paul Berry2013-04-091-7/+6
| | | | | | | | | | | | | Gen7.5 (Haswell) hardware supports primitive restart for all primitive types. It also handles all possible primitive restart indices. Rather than specialize both can_cut_index_handle_restart_index() and the switch statement in can_cut_index_handle_prims() for Haswell, just return early if the hardware is Haswell because we know it can handle everything. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Only use brw_draw.c's trim() function when necessary.Paul Berry2013-04-091-2/+14
| | | | | | | | | | | | | | | | | | | | brw_draw.c contains a trim() function which modifies the vertex count for quads and quad strips in order to discard dangling vertices. In principle this shouldn't be necessary, since hardware since Gen4 is capable of discarding dangling vertices by itself. However, it's necessary because as a hack to speed up rendering on Gen 4-5, we sometimes convert quads to trifans and quad strips to tristrips. The trim() function isn't necessary on Gen6 and up. This patch documents why and when the trim() function is necessary, and avoids calling it when it's not needed. This will avoid creating problems when we enable hardware support for primitive restart of quads and quad strips on Haswell. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965/vs: Fix DEBUG_SHADER_TIME when VS terminates with 2 URB writes.Paul Berry2013-04-091-4/+2
| | | | | | | | | | | The call to emit_shader_time_end() before the second URB write was conditioned with "if (eot)", but eot is always false in this code path, so emit_shader_time_end() was never being called for vertex shaders that performed 2 URB writes. Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* st/vdpau: fix subtitle related bug v2Christian König2013-04-091-0/+4
| | | | | | | | | | Drawing subtitles didn't increased the dirty area of the surface. Reported and tested by freeedrich on irc. v2: don't clear the surface Signed-off-by: Christian König <[email protected]>
* glsl/linker: Reduce scope of non-flat integer varying fix.Paul Berry2013-04-091-4/+3
| | | | | | | | | | | | | | In the mailing list discussion of "glsl/linker: fix varying packing for non-flat integer varyings." (commit 7862bde), we concluded that since the bug only applies to integral variables, it is safer to just apply the bug fix to integer varyings. I forgot to make the change before pushing the patch upstream. (Note: we aren't aware of any bugs in commit 7862bde; it just seems wise to be on the safe side). This patch makes the change. Assuming commit 7862bde gets cherry-picked back to 9.1, this commit should be cherry-picked too. NOTE: This is a candidate for the 9.1 release branch.
* glsl/linker: Adapt flat varying handling in preparation for geometry shaders.Paul Berry2013-04-091-10/+20
| | | | | | | | | | | | | | | | When a varying is consumed by transform feedback, but is not used by the fragment shader, assign_varying_locations() sets its interpolation type to "flat" in order to ensure that lower_packed_varyings never has to deal with non-flat integral varyings (the GLSL spec doesn't require integral vertex outputs to be flat if they aren't consumed by the fragment shader). A similar situation will arise when geometry shader support is added, since the GLSL spec only requires integral vertex shader outputs to be flat when they are consumed by the fragment shader. This patch modifies the linker to handle this situation too. Reviewed-by: Jordan Justen <[email protected]>
* glsl: Document lower_packed_varyings' "flat" requirement with an assert.Paul Berry2013-04-091-0/+8
| | | | | | | | | | | | | To minimize the variety of type conversions that lower_packed_varyings needs to perform, it assumes that integral varyings are always qualified as "flat". link_varyings.cpp takes care of ensuring that this is the case (even in the circumstances where GLSL doesn't require it). This patch documents the assumption with an assertion, for ease in future debugging. Reviewed-by: Jordan Justen <[email protected]>
* glsl/linker: fix varying packing for non-flat integer varyings.Paul Berry2013-04-091-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit dfb57e7 (glsl: Fix error checking on "flat" keyword to match GLSL ES 3.00, GLSL 1.50) relaxed the rules for integral varyings: they only need to be declared as "flat" if they are a fragment shader inputs. This allowed for the possibility of a vertex shader output being a non-flat integer, provided that it was not matched to a fragment shader input. A non-contrived situation where this might arise is if a vertex shader generates some integral outputs which are consumed by tranform feedback, but not by the fragment shader. Unfortunately, lower_packed_varyings assumes that *all* integral varyings are flat, regardless of whether they are consumed by the fragment shader. As a result, attempting to create a non-flat integral vertex output of a size that required packing (i.e. a size other than ivec4 or uvec4) would cause an assertion failure in lower_packed_varyings. This patch prevents the assertion failure by forcing vertex shader outputs to be "flat" whenever they are not consumed by the fragment shader. This should have no effect on rendering since the "flat" keyword only affects the behaviour of fragment shader inputs. Fixes piglit test "spec/EXT_transform_feedback/nonflat-integral". NOTE: This is a candidate for the 9.1 release branch. Reviewed-by: Jordan Justen <[email protected]>
* glsl: Check the size of ir_print_visitor's mode[] array with STATIC_ASSERT.Paul Berry2013-04-092-1/+3
| | | | | | | | | ir_print_visitor::visit(ir_variable *)'s mode[] array needs to match the declaration of the enum ir_variable_mode. It's hard to verify that at compile time, but at least we can use a STATIC_ASSERT to make sure it's the right size. This required adding ir_var_mode_count to the enum.
* glsl: Fix ir_print_visitor's handling of interpolation qualifiers.Paul Berry2013-04-092-2/+5
| | | | | | | | | | | This patch updates the interp[] array to match the enum glsl_interp_qualifier. Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> v2: Add a STATIC_ASSERT to make sure the array is the correct size. This required adding INTERP_QUALIFIER_COUNT to the enum.
* autotools: Better describe which cases OProfileJIT is required.Johannes Obermayr2013-04-091-2/+6
| | | | Signed-off-by: José Fonseca <[email protected]>
* softpipe: misc updates to image dumping in softpipe_flush()Brian Paul2013-04-091-3/+4
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* tgsi: Ensure struct tgsi_ind_register field Index is initialized.Vinson Lee2013-04-081-0/+1
| | | | | | | Fixes uninitialized scalar variable defect reported by Coverity. Signed-off-by: Vinson Lee <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* r600g: Fix UMAD on CaymanMartin Andersson2013-04-091-13/+32
| | | | | | | | | | | | The multiplication part of tgsi_umad did not work on Cayman, because it did not populate the correct vector slots. This fixed hardlocks in the EXT_transform_feedback/order tests. NOTE: This is a candidate for the stable branches. (might not be easy to cherry-pick though) Signed-off-by: Marek Olšák <[email protected]>
* intel: Remove the texture_tiling driconf option.Kenneth Graunke2013-04-084-11/+1
| | | | | | | | | | | | This option can force textures to be untiled. However, on Gen6+, depth buffers must be Y-tiled. MSAA buffers also must be Y-tiled. So setting this option on even a trivial application like glxgears causes assertion failures in a debug build, and likely GPU hangs in a release build. It's just giving users a license to shoot themselves in the foot. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Prefer Y-tiling on Gen6+.Kenneth Graunke2013-04-081-1/+1
| | | | | | | | | | | | | | | | | In the past, we preferred X-tiling for color buffers because our BLT code couldn't handle Y-tiling. However, the BLT paths have been largely replaced by BLORP on Gen6+, which can handle any kind of tiling. We hadn't measured any performance improvement in the past, but that's probably because compressed textures were all untiled anyway. Improves performance in GLB27_TRex_C24Z16_FixedTime by 7.69231%. v2: Rebase on top of Eric's untiled-for-larger-than-aperture changes. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Use tiling even for compressed textures.Kenneth Graunke2013-04-081-1/+1
| | | | | | | | | | | | | | The code has no rationale for why we would force compressed textures to be untiled, and it appears to work fine. Git archeology indicates that it's been that way dating back to when we first started tiling. Improves performance in GLB27_TRex_C24Z16_FixedTimeStep at 1280x720 by 10.0529% +/- 0.573075% (n=12). Improves performance in Xonotic by 4.56409% +/- 0.27965% (n=3). Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* intel: Refactor selection of miptree tilingChad Versace2013-04-081-42/+61
| | | | | | | | | | | | | | | | | | This patch (1) extracts from intel_miptree_create() the spaghetti logic that selects the tiling format, (2) rewrites that spaghetti into a lucid form, and (3) moves it to a new function, intel_miptree_choose_tiling(). No behavioral change. As a bonus, it is now evident that the force_y_tiling parameter to intel_miptree_create() does not really force Y tiling. v2 (Ken): Rebase on top of Eric's untiled-for-larger-than-aperture changes. This required passing in the miptree. Signed-off-by: Chad Versace <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* intel: Allocate hiz in intel_renderbuffer_move_to_temp()Chad Versace2013-04-081-0/+4
| | | | | | | | | | | | | When moving the renderbuffer to a new miptree, we neglected to allocate the hiz buffer for the new miptree. Oops. Fixes all Piglit depthstencil-render-miplevels tests from crash to pass on Sandybridge. Note: This is a candidate for the 9.1 branch. Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Paul Berry <[email protected]> Signed-off-by: Chad Versace <[email protected]>
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