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* radeonsi: rename readonly_memory -> can_speculateMarek Olšák2017-05-294-20/+20
| | | | | | | This is more accurate. Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: fix a crash in si_destroy_context if we fail earlyMarek Olšák2017-05-291-1/+2
| | | | | Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* util: slab_destroy_child should check whether it's been initializedMarek Olšák2017-05-291-0/+3
| | | | | Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radv: Also signal fence if vkAcquireNextImageKHR returns VK_SUBOPTIMAL_KHR.Bas Nieuwenhuizen2017-05-291-1/+1
| | | | | | | It is a successful return. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* freedreno: fix fence creation fail if no renderingRob Clark2017-05-281-13/+1
| | | | | | | | | Android tries to create a FENCE_FD fence without any rendering. And then falls over when that fails. So just always create an initial batch. Fixes: e4ad8695 ("freedreno: fix crash when flush() but no rendering") Signed-off-by: Rob Clark <[email protected]>
* radeonsi: drop useless memcmp() check in si_set_blend_color()Samuel Pitoiset2017-05-271-3/+0
| | | | | | | | | cso_set_blend_color() already checks if the old state is different. Only Nine uses pipe::set_blend_color() directly but I guess it should use the cache too. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* llvmpipe: add LP_NEW_GS flag for updating vertex infoRoland Scheidegger2017-05-271-0/+1
| | | | | | | | | | The vertex information we compute here is really dependent on the last stage before FS. It just happened to work most of the time because new GS tend to come with new VS and/or FS... (The LP_NEW_GS flag was previously set but never used.) Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Jose Fonseca <[email protected]>
* svga: document some incorrect VGPU10 shader translation issuesBrian Paul2017-05-261-0/+9
| | | | | | | | | We have a few mistakes in our shader translation code, but the virtual GPU is forgiving. Reviewed-by: Michal Krol <[email protected]> Reviewed-by: Neha Bhende<[email protected]> Reviewed-by: Jose Fonseca <[email protected]>
* i965/copy_image: Use the blitter on gen5Jason Ekstrand2017-05-261-1/+1
| | | | | | | This was just an accidental typo in the refactoring. The intention was to try the blitter on gen4-5, not just gen4. Reviewed-by: Matt Turner <[email protected]>
* osmesa: link with libunwind if enabled (v2)Alexandre Demers2017-05-261-1/+2
| | | | | | | | | | | | | | | | | | | | | Fixes linking error in libOSmesa when using libunwind. CXXLD libOSMesa.la src/gallium/auxiliary/.libs/libgallium.a(u_debug_stack.o): In function `symbol_name_cached': ./src/gallium/auxiliary/util/u_debug_stack.c:87: undefined reference to `_ULx86_64_get_proc_name' src/gallium/auxiliary/.libs/libgallium.a(u_debug_stack.o): In function `debug_backtrace_capture': ./src/gallium/auxiliary/util/u_debug_stack.c:114: undefined reference to `_Ux86_64_getcontext' ./src/gallium/auxiliary/util/u_debug_stack.c:115: undefined reference to `_ULx86_64_init_local' ./src/gallium/auxiliary/util/u_debug_stack.c:117: undefined reference to `_ULx86_64_step' ./src/gallium/auxiliary/util/u_debug_stack.c:123: undefined reference to `_ULx86_64_get_reg' ./src/gallium/auxiliary/util/u_debug_stack.c:124: undefined reference to `_ULx86_64_get_proc_info' ./src/gallium/auxiliary/util/u_debug_stack.c:120: undefined reference to `_ULx86_64_step' collect2: error: ld returned 1 exit status v2 : Fixes title and adds the original error it is fixing. Signed-off-by: Alexandre Demers <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* i965/blorp: Support copyteximage on gen4-5Jason Ekstrand2017-05-261-4/+7
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Use blorp for CopyImageSubData on gen4-5Jason Ekstrand2017-05-261-123/+17
| | | | | | | | We keep the blit path because it's probably faster when it works. However, now that we can use blorp, we can delete that nasty CPU fall-back path. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Round copy size to the nearest block in intel_miptree_copyJason Ekstrand2017-05-261-2/+2
| | | | | | | | | | | The width and height of the copy don't have to be aligned to the block size if they specify the right or bottom edges of the image. (See also the comment and asserts right above). We need to round them up when we do the division in order to get it 100% right. Reviewed-by: Ben Widawsky <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Cc: "17.0 17.1" <[email protected]>
* i965: Use BLORP for color clears on gen4-5Jason Ekstrand2017-05-262-2/+5
| | | | | | | | We don't support replicated data clears yet. Those take a bit more work and enabling replicated data clears in its own commit is probably better for bisectibility anyway. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Use blorp for color blits on gen4-5Jason Ekstrand2017-05-262-53/+30
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/blorp: Assert that no one tries to blit combined depth stencilJason Ekstrand2017-05-261-0/+6
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Add blorp support for gen4-5Jason Ekstrand2017-05-2610-15/+322
| | | | | | | | | | Due to complications with things such as URB setup on gen4-5, it's easier to keep gen4 support in blorp completely internal to i965. This makes things a bit awkward because that means there's a file in i965 that includes blorp_priv.h but it's either that or have a file in blorp that includes brw_context.h. Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/blorp: Set additional brw_wm_prog_key fields on gen4-5Jason Ekstrand2017-05-262-2/+9
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/gen4: Expose the guts of URB recalculation as a helperJason Ekstrand2017-05-262-5/+12
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/blorp: Add support for gen4-5 SF programsJason Ekstrand2017-05-267-4/+87
| | | | | | | | As part of enabling support for SF programs, we plumb the SF URB size through to emit_urb_config. For now, it's always zero but, on gen4, it may be something larger. Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/blorp: Make convert_to_single_slice available outside blorp_blitJason Ekstrand2017-05-262-8/+11
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/blorp: Use designated initializers to set up VERTEX_ELEMENTSJason Ekstrand2017-05-261-32/+43
| | | | | | | | We also add a slot variable and use it as an iterator. This will make it much easier to conditionally put something between the header and the vertex position. Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/blorp: Rename emit_viewport_state to emit_cc_viewportJason Ekstrand2017-05-261-3/+3
| | | | | | | The real point of this packet is that it sets up CC_VIEWPORT so that name is a bit better. Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/blorp: Make the common genX_blorp_exec code gen4-safeJason Ekstrand2017-05-261-8/+36
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/blorp: Re-arrange blorp_genX_exec.hJason Ekstrand2017-05-261-229/+229
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/blorp: Don't use ffma directlyJason Ekstrand2017-05-261-1/+1
| | | | | | | It isn't supported prior to gen6 and, on gen6+, NIR will fuse the fmul and fadd into an ffma automatically for us anyway. Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/blorp: Delete isl_to_gen_ds_surfypeJason Ekstrand2017-05-261-19/+0
| | | | | | It's no longer used. Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/blorp: Pull the pipeline bits of blorp_exec into a helperJason Ekstrand2017-05-261-25/+31
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/blorp/blit: Add support for normalized coordinatesJason Ekstrand2017-05-262-5/+28
| | | | | | | Gen5 and earlier can't do non-normalized coordinates so we need to compensate in the shader. Fortunately, it's pretty easy plumb through. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Move clip program compilation to the compilerJason Ekstrand2017-05-2613-181/+211
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Move SF compilation to the compilerJason Ekstrand2017-05-2610-246/+209
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/clip: Make brw_clip_prog_key::interp_mode an arrayJason Ekstrand2017-05-262-2/+6
| | | | | | | | | Having it be a pointer means that we end up caching clip programs based on a pointer to wm_prog_data rather than the actual interpolation modes. We've been caching one clip program per FS ever since 91d61fbf7cb61a44a where Timothy rewrote brw_setup_vue_interpolation(). Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/sf: make brw_sf_prog_key::interp_mode an arrayJason Ekstrand2017-05-262-2/+6
| | | | | | | | | Having it be a pointer means that we end up caching clip programs based on a pointer to wm_prog_data rather than the actual interpolation modes. We've been caching one clip program per FS ever since 91d61fbf7cb61a44a where Timothy rewrote brw_setup_vue_interpolation(). Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/compiler: Make brw_disasm take const assemblyJason Ekstrand2017-05-263-15/+15
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/decoder: Handle the BLT ring in gen_group_get_lengthJason Ekstrand2017-05-261-0/+4
| | | | Reviewed-by: Jordan Justen <[email protected]>
* intel/decoder: Handle gen4 VF_STATISTICS and PIPELINE_SELECTJason Ekstrand2017-05-261-2/+7
| | | | | | | These need special handling because they have no "DWord Length" parameter and they have an unusual bias of 1. Reviewed-by: Jordan Justen <[email protected]>
* intel/genxml: Rename 3DSTATE_AA_LINE_PARAMS on gen5Jason Ekstrand2017-05-261-1/+1
| | | | | | All of the other gens use "PARAMETERS". Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/genxml: Use the right subtype for VF_STATISTICS on gen4Jason Ekstrand2017-05-261-1/+1
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/genxml: Iron Lake doesn't support non-normalized sampler coordinatesJason Ekstrand2017-05-261-1/+0
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/genxml: Add SAMPLER_STATE to gen 4.5Jason Ekstrand2017-05-261-0/+63
| | | | | | Somehow this got missed. Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/genxml: Rename the CC_VIEWPORT pointer on gen4-5Jason Ekstrand2017-05-263-3/+3
| | | | | | | It isn't a pointer to "color calc state", that's the packet it's in. It's a pointer to the CC viewport state. Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/genxml: Sampler state is a pointer on gen4-5Jason Ekstrand2017-05-264-10/+10
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/genxml: Suffix KSP0 fields on Iron LakeJason Ekstrand2017-05-261-5/+5
| | | | | | | | | Iron Lake introduced the multiple KSP thing and so you have KSP0-3. However, the genxml didn't have an index on the first "Kernel Start Pointer" or "GRF Register Count". Add one to match gen6+. While we're here, we drop the brackets from the other "GRF Register Count" fields. Reviewed-by: Matt Turner <[email protected]>
* intel/genxml: Make a bunch of things offsets on gen4-5Jason Ekstrand2017-05-263-15/+15
| | | | | | | | | Most things on gen4-5 are addresses because we don't have dynamic state base address and we don't have instruction state base on gen4. However, whoever converted things to addresses got a little over-excited and converted too much. Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/isl: Add gen4_filter_tilingJason Ekstrand2017-05-263-2/+57
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/isl: Add support for setting component write disablesJason Ekstrand2017-05-262-0/+26
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/isl: Add support for gen4 cube maps to get_image_offset_saJason Ekstrand2017-05-261-5/+18
| | | | | | | Gen4 cube maps are a 2-D surface with ISL_DIM_LAYOUT_GEN4_3D which is a bit weird but accurate none the less. Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/isl: Don't request space for stencil/hiz packets unless neededJason Ekstrand2017-05-261-7/+6
| | | | | | | On Iron Lake, the packets exist but we never emit them so there's no need for us to ask the driver to make batch space for them. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/blorp: Properly handle mt->first_levelJason Ekstrand2017-05-261-0/+3
| | | | | | | | The guts of blorp and ISL don't understand i965's partial miptrees. Instead, we need to subtract off first_level before we hand anything off to blorp. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/miptree: Take first_level into account when converting to ISLJason Ekstrand2017-05-261-1/+1
| | | | | | | ISL doesn't have a concept of a partial miptree. Instead, we need to subtract off first_level. Reviewed-by: Topi Pohjolainen <[email protected]>
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