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* radv/sqtt: describe begin/end command buffers with user markersSamuel Pitoiset2020-03-103-0/+108
| | | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4031>
* radv: initial implementation of the driver internal layer SQTTSamuel Pitoiset2020-03-103-0/+347
| | | | | | | | | | This layer is used to emit SQTT user markers to command buffers. It currently only emits API markers but it will consolidated soon with barrier markers and more. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4031>
* radv/sqtt: add a helper that emits thread trace userdata markersSamuel Pitoiset2020-03-102-0/+19
| | | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4031>
* radv: use device entrypoints from the SQTT layer if enabledSamuel Pitoiset2020-03-101-0/+11
| | | | | | | | | This allows to override RADV device entrypoints if the prefix is 'sqtt' instead of 'radv'. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4031>
* radv/entrypoints: declare a driver internal layer for SQTTSamuel Pitoiset2020-03-101-3/+2
| | | | | | | | | | | Some Vulkan commands will be overriden to emit user SQTT markers. These markers are then used by the Radeon GPU Profiler to display timings, barrier operations (cache flushes, pipeline stalls, layout transitions) and more. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4031>
* panfrost: Pass the sampler view format when creating a tex descriptorBoris Brezillon2020-03-101-1/+1
| | | | | | | | | | | A sampler can use a different format than the native texture format. Let's pass the sampler format instead of the native texture format when creating a texture descriptor. Signed-off-by: Boris Brezillon <[email protected]> Reviewed-by: Alyssa Rosenzweig <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4101> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4101>
* Revert "panfrost: Z24 variants should be sampled as R32UI"Boris Brezillon2020-03-102-51/+1
| | | | | | | | | | | | | Commit 0406ea485649 ("panfrost: Z24 variants should be sampled as R32UI") causes a regression when depth textures are sampled. It's still not clear how MALI_Z32 can work for for Z32 and Z24{S,X}8, but let's leave that question for later. Reported-by: Icecream95 <[email protected]> Signed-off-by: Boris Brezillon <[email protected]> Reviewed-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4101>
* gallium: Add forgotten docs for new CAPs related to transform feedbackTomeu Vizoso2020-03-101-0/+3
| | | | | | | | | | These three caps were missing docs. Signed-off-by: Tomeu Vizoso <[email protected]> Reviewed-by: Alyssa Rosenzweig <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4115> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4115>
* lima: enable minmax cache for index buffersVasily Khoruzhick2020-03-103-3/+34
| | | | | | | | | Re-use minmax cache for index buffers from panfrost. Reviewed-by: Andreas Baierl <[email protected]> Signed-off-by: Vasily Khoruzhick <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4051> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4051>
* panfrost: split index cache into shared partVasily Khoruzhick2020-03-107-91/+190
| | | | | | | | | Split it into shared part since we're going to re-use it in lima. Reviewed-by: Alyssa Rosenzweig <[email protected]> Reviewed-by: Boris Brezillon <[email protected]> Signed-off-by: Vasily Khoruzhick <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4051>
* st/mesa: fix a possible crash with selection and feedback modesMarek Olšák2020-03-091-1/+1
| | | | | | | | The index bounds are always valid without an index buffer, but they won't be. Reviewed-by: Dave Airlie <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3986> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3986>
* st/mesa: flush the bitmap cache before st/dri and vbo flushesMarek Olšák2020-03-092-2/+7
| | | | | Reviewed-by: Dave Airlie <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3986>
* intel/fs: Fix workaround for VxH indirect addressing bug under control flow.Francisco Jerez2020-03-101-10/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current workaround for this hardware bug involved marking the ADD instruction used to initialize the address register as NoMask on Gen12, which was based on the assumption that the problem was caused by a hardware bug affecting the application of the execution mask to the address register write. However that doesn't seem to be the case: The address register write was working correctly, the real problem leading to hangs on TGL is that the indirect addressing logic is unable to deal with garbage values in the address register (e.g. misaligned offsets), even for channels which are currently inactive due to non-uniform control flow. The current workaround isn't able to avoid that situation in general, since the result of the NoMask ADD instruction for a dead channel is calculated based on the corresponding (dead) component of the indirect_byte_offset source, which would still be undefined in the likely case that the source was initialized under control flow itself. This would lead to hangs whenever MOV_INDIRECT was used under non-uniform control flow in some scenarios like a tessellation shader from GFXBench5/gl_4 (AKA Car Chase) on TGL. In addition I've managed to reproduce the same issue on earlier platforms by initializing the whole address register with garbage before the ADD instruction, so this seems to be a long-standing issue we have avoided mostly by luck. This patch fixes the problem and applies the workaround to all platforms, since even when the hardware is able to deal with garbage address values without hanging there might be a significant performance cost from reading random GRF registers due to the useless extra EU cycles spent fetching registers for dead channels and due to the potential for unintended serialization with respect to other random instructions that could be executed in parallel, which may have had a cost of the order of hundreds of cycles in the worst case scenario. Fixes: f93dfb509c "intel/fs: Write the address register with NoMask for MOV_INDIRECT" Tested-by: Rafael Antognolli <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* intel/fs: Allow NOT instructions in conditional discard optimizationIan Romanick2020-03-091-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | I don't know why I explicitly disallowed NOT in the first place. :( All Intel platforms had similar results. (Ice Lake shown) total instructions in shared programs: 14549846 -> 14549770 (<.01%) instructions in affected programs: 12934 -> 12858 (-0.59%) helped: 76 HURT: 0 helped stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1 helped stats (rel) min: 0.13% max: 5.56% x̄: 1.04% x̃: 0.90% 95% mean confidence interval for instructions value: -1.00 -1.00 95% mean confidence interval for instructions %-change: -1.25% -0.84% Instructions are helped. total cycles in shared programs: 203793967 -> 203792696 (<.01%) cycles in affected programs: 77920 -> 76649 (-1.63%) helped: 67 HURT: 1 helped stats (abs) min: 2 max: 36 x̄: 19.00 x̃: 16 helped stats (rel) min: 0.04% max: 4.68% x̄: 2.35% x̃: 2.28% HURT stats (abs) min: 2 max: 2 x̄: 2.00 x̃: 2 HURT stats (rel) min: 0.03% max: 0.03% x̄: 0.03% x̃: 0.03% 95% mean confidence interval for cycles value: -20.75 -16.63 95% mean confidence interval for cycles %-change: -2.57% -2.05% Cycles are helped. Reviewed-by: Matt Turner <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3965> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3965>
* intel/fs: Do cmod prop again after schedulingIan Romanick2020-03-091-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pre-RA scheduling can create more opportunities for CMOD propagation. This takes advantage of that. It may be worth doing this again in post-RA scheduling, but there are additional problems there. I'm a little torn about the use of the OPT() macro. On the one hand, it would be confusing to see dumps from INTEL_DEBUG=optimizer that don't match the final output. On the other hand, since register allocation can fail, the same pass can be run multiple times. Each time one or both passes might or might not make progress. This would also lead to incongruous, confusing output. Ice Lake total instructions in shared programs: 14549808 -> 14548529 (<.01%) instructions in affected programs: 231985 -> 230706 (-0.55%) helped: 632 HURT: 0 helped stats (abs) min: 1 max: 32 x̄: 2.02 x̃: 1 helped stats (rel) min: 0.05% max: 2.56% x̄: 0.57% x̃: 0.41% 95% mean confidence interval for instructions value: -2.25 -1.79 95% mean confidence interval for instructions %-change: -0.61% -0.54% Instructions are helped. total cycles in shared programs: 203770850 -> 203776599 (<.01%) cycles in affected programs: 2495653 -> 2501402 (0.23%) helped: 282 HURT: 197 helped stats (abs) min: 1 max: 242 x̄: 20.37 x̃: 16 helped stats (rel) min: <.01% max: 11.65% x̄: 0.91% x̃: 0.64% HURT stats (abs) min: 2 max: 609 x̄: 58.35 x̃: 20 HURT stats (rel) min: <.01% max: 10.97% x̄: 1.35% x̃: 0.66% 95% mean confidence interval for cycles value: 5.27 18.73 95% mean confidence interval for cycles %-change: -0.16% 0.21% Inconclusive result (%-change mean confidence interval includes 0). LOST: 0 GAINED: 2 Skylake total instructions in shared programs: 13447708 -> 13446594 (<.01%) instructions in affected programs: 216813 -> 215699 (-0.51%) helped: 623 HURT: 0 helped stats (abs) min: 1 max: 32 x̄: 1.79 x̃: 1 helped stats (rel) min: 0.06% max: 2.86% x̄: 0.59% x̃: 0.42% 95% mean confidence interval for instructions value: -1.99 -1.59 95% mean confidence interval for instructions %-change: -0.63% -0.55% Instructions are helped. total cycles in shared programs: 193759224 -> 193762726 (<.01%) cycles in affected programs: 2540035 -> 2543537 (0.14%) helped: 249 HURT: 190 helped stats (abs) min: 2 max: 196 x̄: 16.67 x̃: 14 helped stats (rel) min: <.01% max: 4.71% x̄: 0.66% x̃: 0.62% HURT stats (abs) min: 2 max: 614 x̄: 40.27 x̃: 14 HURT stats (rel) min: 0.02% max: 5.78% x̄: 0.86% x̃: 0.37% 95% mean confidence interval for cycles value: 2.57 13.39 95% mean confidence interval for cycles %-change: -0.11% 0.11% Inconclusive result (%-change mean confidence interval includes 0). LOST: 0 GAINED: 1 Broadwell total instructions in shared programs: 13418631 -> 13417393 (<.01%) instructions in affected programs: 243192 -> 241954 (-0.51%) helped: 694 HURT: 0 helped stats (abs) min: 1 max: 31 x̄: 1.78 x̃: 1 helped stats (rel) min: 0.06% max: 2.86% x̄: 0.59% x̃: 0.44% 95% mean confidence interval for instructions value: -1.95 -1.62 95% mean confidence interval for instructions %-change: -0.62% -0.55% Instructions are helped. total cycles in shared programs: 200822940 -> 200829128 (<.01%) cycles in affected programs: 2128651 -> 2134839 (0.29%) helped: 251 HURT: 226 helped stats (abs) min: 1 max: 200 x̄: 14.32 x̃: 12 helped stats (rel) min: <.01% max: 3.56% x̄: 0.60% x̃: 0.50% HURT stats (abs) min: 2 max: 611 x̄: 43.28 x̃: 18 HURT stats (rel) min: 0.02% max: 7.03% x̄: 0.93% x̃: 0.54% 95% mean confidence interval for cycles value: 7.44 18.50 95% mean confidence interval for cycles %-change: 0.02% 0.23% Cycles are HURT. Haswell and Ivy Bridge had similar results. (Haswell shown) total instructions in shared programs: 11569710 -> 11568829 (<.01%) instructions in affected programs: 147862 -> 146981 (-0.60%) helped: 487 HURT: 0 helped stats (abs) min: 1 max: 34 x̄: 1.81 x̃: 1 helped stats (rel) min: 0.12% max: 4.75% x̄: 0.57% x̃: 0.45% 95% mean confidence interval for instructions value: -2.03 -1.59 95% mean confidence interval for instructions %-change: -0.61% -0.54% Instructions are helped. total cycles in shared programs: 187079425 -> 187079437 (<.01%) cycles in affected programs: 1088494 -> 1088506 (<.01%) helped: 234 HURT: 124 helped stats (abs) min: 2 max: 282 x̄: 22.66 x̃: 16 helped stats (rel) min: 0.03% max: 7.88% x̄: 0.93% x̃: 0.75% HURT stats (abs) min: 1 max: 276 x̄: 42.86 x̃: 20 HURT stats (rel) min: 0.03% max: 6.70% x̄: 0.99% x̃: 0.53% 95% mean confidence interval for cycles value: -5.54 5.61 95% mean confidence interval for cycles %-change: -0.41% -0.11% Inconclusive result (value mean confidence interval includes 0). total spills in shared programs: 7746 -> 7740 (-0.08%) spills in affected programs: 6 -> 0 helped: 1 HURT: 0 total fills in shared programs: 6264 -> 6258 (-0.10%) fills in affected programs: 6 -> 0 helped: 1 HURT: 0 Sandy Bridge total instructions in shared programs: 10688576 -> 10688177 (<.01%) instructions in affected programs: 137875 -> 137476 (-0.29%) helped: 358 HURT: 0 helped stats (abs) min: 1 max: 9 x̄: 1.11 x̃: 1 helped stats (rel) min: 0.15% max: 1.43% x̄: 0.35% x̃: 0.28% 95% mean confidence interval for instructions value: -1.18 -1.05 95% mean confidence interval for instructions %-change: -0.37% -0.32% Instructions are helped. total cycles in shared programs: 153397144 -> 153393046 (<.01%) cycles in affected programs: 1220713 -> 1216615 (-0.34%) helped: 255 HURT: 31 helped stats (abs) min: 1 max: 304 x̄: 16.71 x̃: 16 helped stats (rel) min: <.01% max: 6.70% x̄: 0.41% x̃: 0.31% HURT stats (abs) min: 1 max: 41 x̄: 5.29 x̃: 3 HURT stats (rel) min: 0.02% max: 0.65% x̄: 0.16% x̃: 0.11% 95% mean confidence interval for cycles value: -17.44 -11.22 95% mean confidence interval for cycles %-change: -0.40% -0.29% Cycles are helped. Iron Lake total instructions in shared programs: 8106894 -> 8105529 (-0.02%) instructions in affected programs: 287197 -> 285832 (-0.48%) helped: 1099 HURT: 0 helped stats (abs) min: 1 max: 10 x̄: 1.24 x̃: 1 helped stats (rel) min: 0.16% max: 4.55% x̄: 0.67% x̃: 0.61% 95% mean confidence interval for instructions value: -1.29 -1.19 95% mean confidence interval for instructions %-change: -0.70% -0.64% Instructions are helped. total cycles in shared programs: 188347022 -> 188344266 (<.01%) cycles in affected programs: 3740632 -> 3737876 (-0.07%) helped: 758 HURT: 10 helped stats (abs) min: 2 max: 38 x̄: 3.68 x̃: 2 helped stats (rel) min: <.01% max: 1.00% x̄: 0.12% x̃: 0.08% HURT stats (abs) min: 2 max: 4 x̄: 3.20 x̃: 4 HURT stats (rel) min: 0.03% max: 0.07% x̄: 0.06% x̃: 0.07% 95% mean confidence interval for cycles value: -3.82 -3.35 95% mean confidence interval for cycles %-change: -0.13% -0.11% Cycles are helped. GM45 total instructions in shared programs: 4985449 -> 4984768 (-0.01%) instructions in affected programs: 145154 -> 144473 (-0.47%) helped: 547 HURT: 0 helped stats (abs) min: 1 max: 10 x̄: 1.24 x̃: 1 helped stats (rel) min: 0.16% max: 2.86% x̄: 0.66% x̃: 0.61% 95% mean confidence interval for instructions value: -1.31 -1.18 95% mean confidence interval for instructions %-change: -0.69% -0.62% Instructions are helped. total cycles in shared programs: 128835062 -> 128833144 (<.01%) cycles in affected programs: 2720650 -> 2718732 (-0.07%) helped: 517 HURT: 1 helped stats (abs) min: 2 max: 38 x̄: 3.71 x̃: 2 helped stats (rel) min: <.01% max: 0.89% x̄: 0.11% x̃: 0.07% HURT stats (abs) min: 2 max: 2 x̄: 2.00 x̃: 2 HURT stats (rel) min: 0.04% max: 0.04% x̄: 0.04% x̃: 0.04% 95% mean confidence interval for cycles value: -4.02 -3.39 95% mean confidence interval for cycles %-change: -0.12% -0.10% Cycles are helped. Reviewed-by: Matt Turner <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3965>
* docs: update calendar, add news item, and link releases notes for 19.3.5Eric Engestrom2020-03-093-297/+887
| | | | | Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4121> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4121>
* docs: add release notes for 19.3.5Eric Engestrom2020-03-091-0/+169
| | | | | Signed-off-by: Eric Engestrom <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4121>
* st/nine: Fix incompatible-pointer-types-discards-qualifiers errors.Vinson Lee2020-03-091-2/+2
| | | | | | | | | | | | | | | ../src/gallium/state_trackers/nine/nine_ff.c:129:28: error: initializing 'struct nine_ff_vs_key *' with an expression of type 'const void *' discards qualifiers [-Werror,-Wincompatible-pointer-types-discards-qualifiers] struct nine_ff_vs_key *vs = key; ^ ~~~ ../src/gallium/state_trackers/nine/nine_ff.c:145:28: error: initializing 'struct nine_ff_ps_key *' with an expression of type 'const void *' discards qualifiers [-Werror,-Wincompatible-pointer-types-discards-qualifiers] struct nine_ff_ps_key *ps = key; ^ ~~~ Fixes: fdd96578ef2d ("nine: Add state tracker nine for Direct3D9 (v3)") Signed-off-by: Vinson Lee <[email protected]> Reviewed-by: Andre Heider <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4015> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4015>
* radeonsi: determine uses_bindless_samplers correctlyMarek Olšák2020-03-091-5/+6
| | | | | | Acked-by: Pierre-Eric Pelloux-Prayer <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4079> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4079>
* ac: add a bug workaround for the 100% NGG culling caseMarek Olšák2020-03-091-0/+33
| | | | | | Fixes: 8db00a51f85 - radeonsi/gfx10: implement NGG culling for 4x wave32 subgroups Acked-by: Pierre-Eric Pelloux-Prayer <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4079>
* radeonsi: add a bug workaround for NGG - LATE_ALLOC_GSMarek Olšák2020-03-091-0/+6
| | | | | | Cc: 19.3 20.0 <[email protected]> Acked-by: Pierre-Eric Pelloux-Prayer <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4079>
* radeonsi: enable EXT_texture_shadow_lodSonny Jiang2020-03-092-1/+3
| | | | | | | Signed-off-by: Sonny Jiang <[email protected]> Signed-off-by: Marek Olšák <[email protected]> Acked-by: Pierre-Eric Pelloux-Prayer <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4079>
* egl/android: require ANDROID_native_fence_sync for buffer ageChia-I Wu2020-03-091-1/+12
| | | | | | | | | | | Querying buffer age requires a buffer to be dequeued. But dequeuing without ANDROID_native_fence_sync might imply eglClientWaitSync, which results in a deadlock as the display lock is already held by eglQuerySurface. Signed-off-by: Chia-I Wu <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/221> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/221>
* radv/sqtt: fix RADV_THREAD_TRACE_BUFFER_SIZE spellingEdmondo Tommasina2020-03-091-1/+1
| | | | | | Reviewed-by: Samuel Pitoiset <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4116> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4116>
* docs/releasing: add missing </li> tagsEric Engestrom2020-03-091-20/+20
| | | | | | | Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4094> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4094>
* docs: trivial fix for html structureEric Engestrom2020-03-091-0/+1
| | | | | | Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4094>
* glsl/opt_minmax: Add support for float16Neil Roberts2020-03-091-0/+19
| | | | | | | | Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Alyssa Rosenzweig <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3929> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3929>
* glsl/lower_instructions: Handle fp16 for FDIV_TO_MUL_RCPKristian H. Kristensen2020-03-091-4/+5
| | | | Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3929>
* glsl/lower_instructions: Handle fp16 for MOD_TO_FLOORHyunjun Ko2020-03-091-1/+1
| | | | Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3929>
* glsl/lower_instructions: Use float16 constants when appropriateNeil Roberts2020-03-091-5/+31
| | | | | | | | | | | | | When lowering instructions that involve floating-point constants, pick the appropriate type for the constant so that it will also work with float16 parameters. v2: Use float16_t constructor instead of helper function. Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Alyssa Rosenzweig <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3929>
* glsl/validate: Allow float16 in the expression treeNeil Roberts2020-03-091-27/+18
| | | | | | | | | v2. [Hyunjun Ko ([email protected])] squashed 3 commits into one commit. Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3929>
* glsl: Add type queries for fp16+float and fp16+float+doubleKristian H. Kristensen2020-03-091-0/+16
| | | | | | | Following the is_integer_32_64() convention, add is_float_16_32() and float_16_32_64() for these commonly tested combinations. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3929>
* glsl: Handle fp16 unary operations when lowering matrix operationsHyunjun Ko2020-03-091-0/+3
| | | | | | | Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Alyssa Rosenzweig <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3929>
* glsl: Add ir_unop_f2fmpNeil Roberts2020-03-096-0/+10
| | | | | | | | | | | | This is the same as ir_unop_f2f16 except that it comes with a promise that it is safe to optimise it out if the result is immediately converted back to float32 again. Normally this would be a lossy operation but it is safe to do if the conversion was generated as part of the precision lowering pass. Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3929>
* glsl: Add b2f16 and f162b conversion operationsNeil Roberts2020-03-096-0/+21
| | | | | | Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3929>
* glsl: Add IR conversion ops for 16-bit float typesNeil Roberts2020-03-096-0/+26
| | | | | | | | | Adds ir_unop_f162f and ir_unop_f2f16. Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3929>
* glsl: Expand fp16 to float before constant expression evaluationKristian H. Kristensen2020-03-091-0/+26
| | | | | | | | | | | This way the generated constant folding code doesn't need to understand fp16. All operations have to be expanded to full float for evaulation on the CPU, so we might as well do it up front. As far as GLSL is concerned, fp16 isn't a separate type from float, so everything we're supposed to support for float we need to do for fp16. Reviewed-by: Ian Romanick <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3929>
* glsl: Implement constant propagation for fp16Kristian H. Kristensen2020-03-091-0/+3
| | | | | | | Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3929>
* glsl: Add fp16 case for ir_triop_lrp optimizationKristian H. Kristensen2020-03-091-0/+3
| | | | | | | Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3929>
* glsl: Add support for float16 types in the IR treeNeil Roberts2020-03-095-12/+86
| | | | | | | Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Alyssa Rosenzweig <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3929>
* glsl: Add ir_constant constructor for fp16Kristian H. Kristensen2020-03-093-2/+33
| | | | | Reviewed-by: Ian Romanick <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3929>
* freedreno/ir3: Don't fold conversions into signKristian H. Kristensen2020-03-091-0/+1
| | | | | | Not supported. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3929>
* gitlab-ci: rules:changes to test on tested drivers changesPierre-Eric Pelloux-Prayer2020-03-093-24/+156
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For now tests only use these drivers: * llvmpipe * softpipe * freedreno * lima * etnaviv * panfrost So using rules:changes gitlab feature to run the tests when the changes made are potentially affecting these drivers. A few notes: * the following code: .piglit-test: extends: - .test-gl - .llvmpipe-rules makes gitlab replace .test-gl "rules:changes" values by the one from ".llvmpipe-rules". * rules:changes always matches for non-MR new branches so jobs will always be created (and they'll be run if their dependencies are run). For pushes to existing branches the files changed by the push are used to match the rules:changes path. * the same gitlab feature could be used for some build jobs Acked-by: Eric Engestrom <[email protected]> Reviewed-by: Michel Dänzer <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2569> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2569>
* amd: join emit_kill() from radv and radeonsi in ac_nir_to_llvmDaniel Schürmann2020-03-094-20/+1
| | | | | | Reviewed-by: Marek Olšák <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4047> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4047>
* radv: use nir_lower_discard_to_demote to work around game bugsDaniel Schürmann2020-03-093-0/+6
| | | | | Reviewed-by: Samuel Pitoiset <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4047>
* radeonsi: lower discard to demote when FS_CORRECT_DERIVS_AFTER_KILL is enabledDaniel Schürmann2020-03-095-26/+7
| | | | | Reviewed-by: Marek Olšák <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4047>
* amd/llvm: implement nir_intrinsic_demote(_if) and ↵Daniel Schürmann2020-03-093-11/+132
| | | | | | | | | | nir_intrinsic_is_helper_invocation The current implementation uses a temporary helper variable to ensure correct behavior until LLVM provides an intrinsic. Reviewed-by: Marek Olšák <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4047>
* nir: add pass to lower discard() to demote()Daniel Schürmann2020-03-094-0/+73
| | | | | | | | | This pass is intended to work around game bugs, only! It also lowers nir_intrinsic_load_helper_invocation to nir_intrinsic_is_helper_invocation for consistency. Reviewed-by: Marek Olšák <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4047>
* nir: gather info whether a shader uses demote_to_helperDaniel Schürmann2020-03-092-0/+4
| | | | | Reviewed-by: Marek Olšák <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4047>
* docs: fix typo in v20 release notesEli Schwartz2020-03-091-1/+1
| | | | | | | | | | | | It makes no sense to wait for it to stabilize on a version released months previously in the previous major release cycle. This was probably intended to be recommending the first bugfix release of the current major.minor release cycle. Reviewed-by: Eric Engestrom <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4106> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4106>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-13 01:39:32 +0000