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* intel/compiler: Remove cs_prog_data->threadsCaio Marcelo de Oliveira Filho2020-04-093-23/+3
* iris: Stop using cs_prog_data->threadsCaio Marcelo de Oliveira Filho2020-04-093-8/+12
* anv: Stop using cs_prog_data->threadsCaio Marcelo de Oliveira Filho2020-04-095-6/+32
* i965: Implement ARB_compute_variable_group_sizePlamena Manolova2020-04-0910-9/+103
* intel/compiler: Add support for variable workgroup sizePlamena Manolova2020-04-096-29/+101
* intel/compiler: Replace cs_prog_data->push.total with a helperCaio Marcelo de Oliveira Filho2020-04-097-18/+32
* swr/rasterizer: Use private functions for min/max to avoid namespace issues.Vinson Lee2020-04-091-45/+45
* tu: Implement descriptor set update templatesConnor Abbott2020-04-092-4/+125
* tu: Add missing code for immutable samplersConnor Abbott2020-04-091-0/+20
* tu: Emit CP_LOAD_STATE6 for descriptorsConnor Abbott2020-04-095-5/+304
* tu: Switch to the bindless descriptor modelConnor Abbott2020-04-097-868/+673
* ir3: Rewrite UBO push analysis to support bindlessConnor Abbott2020-04-094-62/+113
* ir3: Plumb through bindless supportConnor Abbott2020-04-0911-99/+526
* ir3: LDC also has a destinationConnor Abbott2020-04-091-1/+1
* ir3: Also don't propagate immediate offset with LDCConnor Abbott2020-04-091-3/+3
* ir3: Plumb through support for a1.xConnor Abbott2020-04-0911-67/+164
* ir3: Add bindless instruction encodingConnor Abbott2020-04-093-103/+277
* freedreno/a6xx: Add registers for the bindless modelConnor Abbott2020-04-092-0/+39
* freedreno/a6xx: Add UBO size fieldConnor Abbott2020-04-091-1/+1
* tu: ir3: Emit push constants directlyConnor Abbott2020-04-096-26/+86
* tu: Dump out shader assembly when requestedConnor Abbott2020-04-091-0/+14
* aco: RA - move all std::function objects into proper functionsDaniel Schürmann2020-04-091-136/+134
* aco: move all needed helper containers to ra_ctxDaniel Schürmann2020-04-091-56/+58
* aco: change live_out variables to std::unordered_setDaniel Schürmann2020-04-094-8/+17
* aco: change some std::map to std::unordered_map in register_allocationDaniel Schürmann2020-04-091-14/+14
* aco: refactor try_remove_trivial_phi() in RADaniel Schürmann2020-04-092-23/+25
* aco: improve speed of live_var_analysisDaniel Schürmann2020-04-091-53/+20
* aco: during RA only insert into renames table if a variable got renamedDaniel Schürmann2020-04-091-18/+11
* aco: replace assignment hashmap by std::vector in register allocationDaniel Schürmann2020-04-091-74/+92
* aco: improve register assignment when live-range splits are necessaryDaniel Schürmann2020-04-091-3/+5
* aco: improve hashing for value numberingDaniel Schürmann2020-04-091-28/+79
* aco: add explicit padding for all Instruction sub-structsDaniel Schürmann2020-04-091-11/+46
* aco: guarantee that Temp fits in 4 bytesDaniel Schürmann2020-04-091-9/+9
* turnip: new clear/blit implementation with shader path fallbackJonathan Marek2020-04-0915-1990/+2578
* turnip: add vk_format_is_snorm/is_floatJonathan Marek2020-04-091-0/+12
* turnip: rework format helpersJonathan Marek2020-04-096-29/+41
* turnip: use dirty bits for dynamic viewport/scissor stateJonathan Marek2020-04-092-8/+16
* turnip: save attachment samples in renderpass stateJonathan Marek2020-04-092-4/+5
* turnip: disable 8x msaaJonathan Marek2020-04-092-5/+6
* turnip: fix nir validate failure from push constant loweringJonathan Marek2020-04-091-0/+3
* turnip: split up gmem/tile alignmentJonathan Marek2020-04-094-20/+12
* turnip: RB_CCU_CNTL fixesJonathan Marek2020-04-094-16/+19
* freedreno/a6xx: set bypass RB_CCU_CNTL value for blitterJonathan Marek2020-04-091-0/+5
* freedreno/registers: add RB_CCU_CNTL bitfieldsJonathan Marek2020-04-094-14/+34
* radv: allow TC-compat HTILE with GENERAL outside of render loopsSamuel Pitoiset2020-04-091-1/+16
* radv: only enable TC-compat HTILE for images readable by a shaderSamuel Pitoiset2020-04-091-0/+8
* radv: only expose fp16 control features for chips with double rate fp16Samuel Pitoiset2020-04-091-5/+10
* radv: only expose storageInputOutput16 for chips with double rate fp16Samuel Pitoiset2020-04-091-2/+2
* radv: only expose shaderFloat16 for chips with double rate fp16Samuel Pitoiset2020-04-092-3/+3
* ac,radv: add ac_gpu_info::has_double_rate_fp16Samuel Pitoiset2020-04-093-2/+6
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