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* intel: Add ISL_AUX_USAGE_GEN12_CCS_ENanley Chery2020-06-196-9/+54
| | | | | | | | | Add a new aux usage which more accurately describes the behavior of CCS_E on gen12. On this platform, writes using the 3D engine are either compressed or substituted with fast-cleared blocks. Reviewed-by: Kenneth Graunke <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5363>
* ci: Enable NIR validation on a630 GLES2 and VK tests.Eric Anholt2020-06-191-1/+4
| | | | | | | | We get through GLES2 in 5.5 minutes and the vk subset in 8 minutes, so we can spare the CPU time on these tests. Acked-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5554>
* ci: Bump vulkan CTS to 1.2.3.0.Eric Anholt2020-06-195-68/+47
| | | | | | | | | | | | | | Looks like it fixes some potentially important VK test bugs. But also, it fixes the GLES31 SSBO layout tests to not be so excessively large, so we can run them in a reasonable time now. Note that a630 fail list is reset, since the test list has changed and so we end up with a different subset of tests being run. Interestingly, in the process the semaphore tests are now reporting "NotSupported (Exporting and importing semaphore type not supported at vktSynchronizationSignalOrderTests.cpp:513)" where they weren't before. Reviewed-by: Samuel Pitoiset <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5554>
* iris: Disable sRGB fast-clears for non-0/1 valuesNanley Chery2020-06-196-41/+20
| | | | | | | | | | | | | | | | | | For texturing and draw calls, HW expects the clear color to be in two different color spaces after sRGB fast-clears - sRGB in the former and linear in the latter. Up until now, iris has stored the clear color in the sRGB color space. Limit the allowable clear colors for sRGB fast-clears to 0/1 so that both color space requirements are satisfied. Makes iris pass the sRGB -> sRGB subtest of the fcc-write-after-clear piglit test on gen9+. v2: * Drop iris_context::blend_enables. (Ken) * Drop some more resolve-related blend-state-tracking code. Reviewed-by: Kenneth Graunke <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4972>
* iris: Avoid fast-clear with incompatible viewNanley Chery2020-06-193-2/+40
| | | | | | | | | | | | | | | | For rendering operations, avoid adding or using fast-cleared blocks if the render format is incompatible with the clear color interpretation. Note that the clear color is currently interpreted through the resource's surface format. Makes iris pass subtests of the fcc-write-after-clear piglit test: * UNORM -> SNORM, partial block on gen8+. * linear -> sRGB, partial block on gen9+. * UNORM -> SNORM, full block on gen12. Reviewed-by: Kenneth Graunke <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4972>
* iris: Remove the CCS_D fallbackNanley Chery2020-06-193-4/+3
| | | | | | | | | | | | | | | | | | | | | | Remove the CCS_D fallback logic so that iris doesn't attempt to use a non-existent surface state for some renders. Also, add an assertion to catch the issue. The fallback in iris_resource_render_aux_usage can lead to this problem because it doesn't account for the fact that surface states created from resources with the Y_TILED_CCS modifier may only have CCS_E or NONE as aux usages (due to iris_resource_create_with_modifiers). Without this change, the next commit would have triggered the fallback and regressed the following tests on gen9: * dEQP-EGL.functional.wide_color.window_888_colorspace_srgb * dEQP-EGL.functional.wide_color.window_8888_colorspace_srgb * dEQP-EGL.functional.wide_color.pbuffer_888_colorspace_srgb * dEQP-EGL.functional.wide_color.pbuffer_8888_colorspace_srgb Reviewed-by: Kenneth Graunke <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4972>
* iris: Drop can_fast_clear_color's format parameterNanley Chery2020-06-191-4/+3
| | | | | | | | Pull the resource's format from the pipe_resource instead. Makes the changes in later commits more obvious. Reviewed-by: Kenneth Graunke <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4972>
* docs: move "stable" tag explanation next to `Fixes:`Eric Engestrom2020-06-191-23/+21
| | | | | | Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5378>
* docs: move `Fixes:` tag explanation to its own sectionEric Engestrom2020-06-191-21/+19
| | | | | | | | | This also adds the ability to link directly to it: https://mesa3d.org/submittingpatches.html#fixes Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5378>
* docs: make it clear that the tags needs to be in the commit messageEric Engestrom2020-06-191-3/+3
| | | | | | | | | Some people have been putting them only in the MR description, which isn't picked up by our tools. (Note that doing both doesn't hurt.) Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5378>
* docs: reword a sentence a bitEric Engestrom2020-06-191-5/+4
| | | | | | | | | The "that you know ahead of time" bit just sounded weird as everything on this page except the backport MR only applies if you know it "ahead of time". Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5378>
* docs: add some formatting to the "backport merge request" optionEric Engestrom2020-06-191-2/+2
| | | | | | Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5378>
* docs: prefer `Fixes:` over `Cc: mesa-stable`Eric Engestrom2020-06-191-3/+4
| | | | | | | | | `Fixes:` targets a specific commit and as such is much more precise and useful than `Cc: mesa-stable`, so let's prefer it when applicable. Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5378>
* docs: drop `git sendemail` instructionsEric Engestrom2020-06-191-14/+0
| | | | | | Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5378>
* docs: reword "sending a patch revision" to "updating a merge request"Eric Engestrom2020-06-191-3/+4
| | | | | | Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5378>
* docs: stop considering `Cc: mesa-stable` as an email addressEric Engestrom2020-06-191-3/+3
| | | | | | | | | Our tools haven't needed more than this ^ for a while, and the historical reasons this used to be an email address don't matter anymore. Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5378>
* freedreno/a6xx: Set index buffer size to bo sizeKristian H. Kristensen2020-06-191-1/+1
| | | | | | | The number of vertices may be out of bound and if we use it for computing index buffer size we may get too big a size. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5552>
* freedreno/a6xx: Don't write REG_A6XX_RB_SRGB_CNTL in restoreKristian H. Kristensen2020-06-191-3/+0
| | | | | | We configure this as part of MRT set up. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5552>
* anv: Use resolve_device_entrypoint for dispatch initJason Ekstrand2020-06-193-51/+17
| | | | | | | | | | | | There's no good reason to have the "which table do I use?" code duplicated twice. The only advantage to the way we were doing it before was that we could move the switch statement outside the loop. If this is ever an actual device initialization perf problem that someone cares about, we can optimize that when the time comes. For now, the duplicated cases are simply a platform-enabling pit-fall. Reviewed-by: Jordan Justen <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5530>
* docs: suggest alternative installation methods for mesonEric Engestrom2020-06-191-1/+8
| | | | | | | | | A couple of popular distros have a habit of never updating anything. Point their users towards ways of using current versions of meson anyway. Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2988>
* turnip: Fill out VkPhysicalDeviceSubgroupPropertiesBrian Ho2020-06-191-0/+10
| | | | | | | | | | | This commit fills out VkPhysicalDeviceSubgroupProperties if present in a VkPhysicalDeviceProperties2. The values here are simply pulled from the blob. Fixes some flakes in dEQP-VK.subgroups.* since dEQP was reading uninitialized values of VkPhysicalDeviceSubgroupProperties. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5564>
* zink: use int assignment for vk int typeMike Blumenkrantz2020-06-191-1/+1
| | | | | | | this breaks 32bit builds that use -Werror=int-conversion Reviewed-by: Erik Faye-Lund <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5545>
* freedreno/ir3: move output_loc to variantRob Clark2020-06-198-37/+40
| | | | | | | | This moves the last bit of important state to be serialized from ir3_shader to ir3_shader_variant. Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5508>
* freedreno/ir3: move const_state back to variantRob Clark2020-06-197-40/+54
| | | | | | | | | | | | | For shader-cache, we want to not have anything important in `ir3_shader`. And to have shader variants with lower const size limits (to properly handle cross-stage limits), we also want variants to be able to have their own const_state. But we still need binning pass shaders to align with their draw pass counterpart so that the same const emit can be used for both passes. Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5508>
* freedreno/ir3: un-embed const_stateRob Clark2020-06-198-10/+21
| | | | | | | | | | | Make it an rzalloc'd ptr instead of embedded struct, so it can serve as the mem ctx for immediates. This gets rid of needing to explicitly free the immediates, so one less thing to deal with when moving const_state. (Also, after we move const_state to the shader variant, we won't need one for binning pass variants) Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5508>
* freedreno/ir3: move num_reserved_user_consts out of const_stateRob Clark2020-06-193-3/+3
| | | | | | | | | When we move const_state to the variant, this will need to stay in the shader, as it applies to all variants (and we need to store it somewhere before we have any variants) Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5508>
* freedreno/ir3: convert over to rallocRob Clark2020-06-193-26/+8
| | | | | | | | | | | The `ir3_shader` is the root mem ctx, with `ir3_shader_variant` hanging off that, and various variant specific allocations hanging off the variant. This lets us delete a bunch of cleanup code. Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5508>
* freedreno/ir3: pass variant to ir3_create()Rob Clark2020-06-194-6/+8
| | | | | | | Prep to convert over to ralloc. Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5508>
* ir3: Split out variant-specific lowering and optimizationsConnor Abbott2020-06-195-96/+109
| | | | | | | | | | | | | | | | | | | | It seems a lot of the lowerings being run the second time were unnecessary. In addition, when const_state is moved to the variant, then it will become impossible to know ahead of time whether a variant needs additional optimizing, which means that ir3_key_lowers_nir() needs to go away. The new approach should have the same effect, since it skips running lowerings that are unnecessary and then skips the opt loop if no optimizations made progress, but it will work better when we move ir3_nir_analyze_ubo_ranges() to be after variant creation. The one maybe controversial thing I did is to make nir_opt_algebraic_late() always happen during variant lowering. I wanted to avoid code duplication, and it seems to me that we should push the _late variants as far back as possible so that later opt_algebraic runs don't miss out on optimization opportunities. Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5508>
* freedreno/ir3: constify shader keyRob Clark2020-06-192-5/+5
| | | | | Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5508>
* freedreno/ir3: drop shader->num_ubosRob Clark2020-06-194-17/+15
| | | | | | | | | | | | | | The only difference between this and `const_state->num_ubos` was that the latter is counting # of ubos loaded via `ldg` (based on UBO addrs in push-consts). But turns out there isn't really any reason to care. Instead just add an early return in the one code-path that cares about the number of `ldg` UBOs. This gets rid of one more thing we need to move from `ir3_shader` to `ir3_shader_variant`. Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5508>
* freedreno/ir3: move ubo_state into const_stateRob Clark2020-06-199-28/+27
| | | | | | | | | As with const_state, this will also need to move into the variant. To simplify that, just move it into the const_state itself, since after all it is related. Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5508>
* freedreno/a6xx: defer userconst cmdstream size calculationRob Clark2020-06-193-25/+25
| | | | | | | | | The `ubo_state` will also need to move to `ir3_shader_variant`. But we can prepare for that and simplify things a bit if we calculate the cmdstream on first emit, once we already have the appropriate variant. Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5508>
* freedreno/ir3: add accessor for const_stateRob Clark2020-06-1910-28/+39
| | | | | | | | | | | | | | We are going to want to move this back to the variant, and come up with a different strategy for binning/nonbinning to share the same constant layout, in order to implement shader-cache support. (Since then we can have a mix of dynamically compiled variants and cache hits, so there is no good place to serialize the const-state.) To reduce the churn as we re-arrange things, move direct access to the const-state to a helper fxn. This patch is the boring churny part. Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5508>
* freedreno/ir3: refactor out helper to compile shader from asmRob Clark2020-06-198-48/+127
| | | | | | | | | Deduplicate a bit of hand-building of ir3_shader/_variant from computerator and delay test. This also removes the need for external things to depend on generated ir3_parser header. Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5508>
* st/mesa: make texture views inherit compressed_data storagePierre-Eric Pelloux-Prayer2020-06-192-6/+27
| | | | | | | Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2775 Fixes: c3fafa127a0 ("st/mesa: generalize code for the compressed texture map/unmap fallback") Reviewed-by: Marek Olšák <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5492>
* ac/llvm: load 1 byte at a time if unaligned on gfx10Pierre-Eric Pelloux-Prayer2020-06-191-1/+1
| | | | | | | | | | | | | | If buffer or stride is unaligned we use the same trick as on gfx6: load 1 byte at a time and recompose the output if needed. This change fixes lots of deqp/glcts tests: - dEQP-GLES2.functional.draw.random.1, 10, ... - dEQP-GLES2.functional.vertex_arrays.multiple_attributes.stride.3_float2_0_float2_0_float2_17, ... - dEQP-GLES2.functional.vertex_arrays.single_attribute.first.byte_first24_offset1_stride2_quads256, ... - dEQP-GLES2.functional.vertex_arrays.single_attribute.strides.buffer_0_17_byte2_vec4_dynamic_draw_quads_1, ... - dEQP-GLES31.functional.draw_indirect.random.14, ... Reviewed-by: Marek Olšák <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5502>
* r600/sfn: Handle memory_barrierGert Wollny2020-06-191-0/+1
| | | | | | | | | I'm not sure whether this should actually be a barrier accross all shader processing units, the TGSI code path seems to handle this only by using GROUP_BARRIER, so let's do the same here. Signed-off-by: Gert Wollny <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5206>
* r600/sfn: Take SSBO buffer ID offset into accountGert Wollny2020-06-194-8/+35
| | | | | Signed-off-by: Gert Wollny <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5206>
* r600/sfn: Add support for reading cube image array dim.Gert Wollny2020-06-193-15/+40
| | | | | | | | The cube array size can't be queried directly, the number of array elements must be passed via a constant buffer. Signed-off-by: Gert Wollny <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5206>
* r600/sfn: Add support for image_sizeGert Wollny2020-06-192-0/+24
| | | | | Signed-off-by: Gert Wollny <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5206>
* r600/sfn: Add imageio supportGert Wollny2020-06-193-47/+325
| | | | | Signed-off-by: Gert Wollny <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5206>
* r600/sfn: lower image derefsGert Wollny2020-06-192-1/+1
| | | | | | | v2: Signal lowering image derefs by using the CAP Signed-off-by: Gert Wollny <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5206>
* radv: require LLVM 11+ for GFX 10.3 if not using ACOSamuel Pitoiset2020-06-191-0/+6
| | | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5389>
* radv: add support for Sienna CichlidSamuel Pitoiset2020-06-195-10/+45
| | | | | | | | Bits copied from RadeonSI. Totally untested. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5389>
* aco: replace == GFX10 with >= GFX10 where it's neededSamuel Pitoiset2020-06-193-7/+7
| | | | | | | | | Assume the GFX10.3 ISA is similar to GFX10 which is likely (except possible minor changes and new instructions for raytracing). Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5389>
* radv: replace == GFX10 with >= GFX10 where it's neededSamuel Pitoiset2020-06-192-3/+3
| | | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5389>
* intel/tools: Add assembler tests for the cr0 registerMatt Turner2020-06-196-0/+70
| | | | | Reviewed-by: Sagar Ghuge <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5514>
* intel/tools: Disallow control subregisters > 3Matt Turner2020-06-191-1/+1
| | | | | | | | > 4 was probably a typo, since the documentation says that there are 4 subregisters (0-3). Reviewed-by: Sagar Ghuge <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5514>
* intel/tools: Require explicit regions/types for special regsMatt Turner2020-06-191-28/+10
| | | | | | | | | | | | The docs say that these registers should only be read with a certain type, and I'm inclined to believe that the hardware behaves that way, but it makes the assembler a little more confusing and also confuses the user of the assembler that some operands don't take types or regions. Just always requiring regions and types seems like the sensible thing. Reviewed-by: Sagar Ghuge <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5514>
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