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* genxml: Make "Reorder Mode" fields consistent.Kenneth Graunke2017-05-033-6/+8
| | | | | | | | Both GS and SOL have these fields. Some were ReorderEnable = true, some were ReorderMode = REORDER_TRAILING, and some were just TRAILING. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Rafael Antognolli <[email protected]>
* genxml: Add alias for MOCS.Rafael Antognolli2017-05-034-0/+4
| | | | | | | | | | | Use an alias, so we can set the same value as the #define's. v3: - Call it "SO Buffer MOCS" to follow the most common naming scheme. - Add alias for gen7 and gen75 too (Ken). Signed-off-by: Rafael Antognolli <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* genxml: Add missing field values to 3DSTATE_SBE.Rafael Antognolli2017-05-031-1/+6
| | | | | | | Fill out "Attribute Active Component Format" possible values. Signed-off-by: Rafael Antognolli <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* genxml: Update xml for 3DSTATE_SF.Rafael Antognolli2017-05-032-6/+16
| | | | | | | | | | - Normalize "Anti-Aliasing Enable" - Add "Multisample Rasterization Mode" constants - Rename "Use Point Width on Vertex" to "Vertex" - Rename "Use Point Width from State" to "State" Signed-off-by: Rafael Antognolli <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* genxml: Rename clip enable property.Rafael Antognolli2017-05-034-4/+4
| | | | | | | | | | | There are two variants: - Clip Enable - CLIP Enable (on gen6) Rename everything to Clip Enable. Signed-off-by: Rafael Antognolli <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* genxml: Fill out Gen4, Gen45 and Gen5 XMLLouis-Francis Ratté-Boulianne2017-05-033-1065/+2517
| | | | | | | | | | | | | | Add some more details to Gen4 and Gen45 and add what is needed in Gen5 XML. This commit overwrite the previous work done on Gen4 and Gen45 as it contains more instructions and fixes some mistakes. However, comments (dword boundaries) are lost in the process. v3: - Set the type of some fields, instead of prefix. Also fix the SAMPLER_BORDER_COLOR_STATE fields of gen5.xml. Signed-off-by: Louis-Francis Ratté-Boulianne <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* anv: Implement VK_KHX_external_semaphore_fdJason Ekstrand2017-05-035-16/+199
| | | | | | | | This implementation allocates a 4k BO for each semaphore that can be exported using OPAQUE_FD and uses the kernel's already-existing synchronization mechanism on BOs. Reviewed-by: Chad Versace <[email protected]>
* anv: Pull the guts of cmd_buffer_execbuf into a helperJason Ekstrand2017-05-031-24/+35
| | | | | Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* anv: Implement VK_KHX_external_semaphoreJason Ekstrand2017-05-033-0/+13
| | | | Reviewed-by: Chad Versace <[email protected]>
* anv: Implement VK_KHX_external_semaphore_capabilitiesJason Ekstrand2017-05-033-0/+18
| | | | | | | This just stubs things out. Real external semaphore support will come with VK_KHX_external_semaphore_fd. Reviewed-by: Chad Versace <[email protected]>
* anv: Add a real semaphore structJason Ekstrand2017-05-032-6/+54
| | | | | | | It's just a dummy for now, but we'll flesh it out as needed for external semaphores. Reviewed-by: Chad Versace <[email protected]>
* radeonsi/gfx9: fix gl_ViewportIndexMarek Olšák2017-05-032-8/+40
| | | | | | | v2: remove unnecessary LLVMBuildAnd calls Cc: 17.1 <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: set VGT_REUSE_OFF = 0Marek Olšák2017-05-031-3/+7
| | | | | | same as Vulkan Reviewed-by: Nicolai Hähnle <[email protected]>
* etnaviv: add L8A8_UNORM texture formatChristian Gmeiner2017-05-031-0/+2
| | | | | | | | No piglit regressions. CC: <[email protected]> Signed-off-by: Christian Gmeiner <[email protected]> Reviewed-by: Philipp Zabel <[email protected]>
* glsl: Corrected some typos and error messagesAndres Gomez2017-05-031-4/+5
| | | | | | | v2: left code style/formatting corrections out. Signed-off-by: Andres Gomez <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* radv: don't leak DRM devicesGrazvydas Ignotas2017-05-031-1/+3
| | | | | | | | After successful drmGetDevices2() call, drmFreeDevices() needs to be called. Fixes: 743315f2 "radv: do not open random render node(s)" Signed-off-by: Grazvydas Ignotas <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: fix possible stack corruptionGrazvydas Ignotas2017-05-031-1/+1
| | | | | | | | | | drmGetDevices2 takes count and not size. Probably hasn't caused problems yet in practice and was missed as setups with more than 8 DRM devices are not very common. Fixes: 743315f2 "radv: do not open random render node(s)" Signed-off-by: Grazvydas Ignotas <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* ac: eliminate duplicated VS exportsMarek Olšák2017-05-031-2/+79
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Only very few shaders have them (from 48486 shaders): shaders/private/left_4_dead_2/765.shader_test - ac: 1 matches 2 shaders/private/left_4_dead_2/877.shader_test - ac: 1 matches 6 shaders/private/left_4_dead_2/2141.shader_test - ac: 1 matches 6 shaders/private/ue4_effects_cave/11.shader_test - ac: 4 matches 5 shaders/private/ue4_effects_cave/14.shader_test - ac: 5 matches 6 shaders/private/ue4_effects_cave/46.shader_test - ac: 5 matches 6 shaders/private/ue4_effects_cave/42.shader_test - ac: 4 matches 5 shaders/private/ue4_effects_cave/104.shader_test - ac: 4 matches 5 shaders/private/f1-2015/336.shader_test - ac: 3 matches 4 shaders/private/f1-2015/948.shader_test - ac: 6 matches 7 shaders/private/f1-2015/602.shader_test - ac: 0 matches 3 shaders/private/f1-2015/600.shader_test - ac: 0 matches 3 shaders/private/f1-2015/1214.shader_test - ac: 0 matches 1 shaders/private/f1-2015/988.shader_test - ac: 4 matches 5 shaders/private/ue4_elemental/149.shader_test - ac: 3 matches 4 shaders/private/ue4_elemental/346.shader_test - ac: 4 matches 5 shaders/private/ue4_elemental/178.shader_test - ac: 3 matches 4 shaders/private/ue4_elemental/136.shader_test - ac: 4 matches 5 shaders/private/ue4_elemental/168.shader_test - ac: 4 matches 5 shaders/private/ue4_elemental/690.shader_test - ac: 3 matches 4 shaders/private/ue4_elemental/19.shader_test - ac: 5 matches 6 shaders/private/dota2/1901.shader_test - ac: 0 matches 5 shaders/private/dota2/1357.shader_test - ac: 0 matches 5 shaders/private/dota2/1375.shader_test - ac: 0 matches 5 shaders/private/dota2/1369.shader_test - ac: 0 matches 5 shaders/private/dota2/1583.shader_test - ac: 0 matches 5 shaders/private/dota2/1811.shader_test - ac: 0 matches 5 shaders/private/dota2/1893.shader_test - ac: 0 matches 5 shaders/private/dota2/1533.shader_test - ac: 0 matches 5 shaders/private/dota2/1951.shader_test - ac: 0 matches 5 shaders/private/dota2/1361.shader_test - ac: 0 matches 5 shaders/private/mad_max/2792.shader_test - ac: 0 matches 1 shaders/private/mad_max/2794.shader_test - ac: 0 matches 1 shaders/private/mad_max/2780.shader_test - ac: 0 matches 1 shaders/private/mad_max/2902.shader_test - ac: 0 matches 1 shaders/private/bioshock-infinite/3050.shader_test - ac: 3 matches 7 shaders/private/bioshock-infinite/2544.shader_test - ac: 3 matches 6 shaders/private/bioshock-infinite/3062.shader_test - ac: 3 matches 8 shaders/private/bioshock-infinite/2012.shader_test - ac: 3 matches 7 shaders/private/bioshock-infinite/3058.shader_test - ac: 3 matches 7 shaders/private/bioshock-infinite/3270.shader_test - ac: 3 matches 7 shaders/private/bioshock-infinite/732.shader_test - ac: 3 matches 7 shaders/private/bioshock-infinite/3026.shader_test - ac: 3 matches 7 shaders/private/bioshock-infinite/3258.shader_test - ac: 3 matches 6 shaders/private/bioshock-infinite/3198.shader_test - ac: 3 matches 6 shaders/private/bioshock-infinite/3046.shader_test - ac: 3 matches 7 shaders/private/bioshock-infinite/3168.shader_test - ac: 3 matches 6 shaders/private/bioshock-infinite/2550.shader_test - ac: 3 matches 6 shaders/private/bioshock-infinite/3210.shader_test - ac: 3 matches 6 shaders/private/bioshock-infinite/3032.shader_test - ac: 3 matches 6 shaders/private/bioshock-infinite/668.shader_test - ac: 3 matches 7 Reviewed-by: Dave Airlie <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* ac: rename ac_eliminate_const_vs_outputs -> ac_optimize_vs_outputsMarek Olšák2017-05-034-20/+20
| | | | | Reviewed-by: Dave Airlie <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* ac: first parse VS exports before eliminating constant onesMarek Olšák2017-05-031-24/+58
| | | | | | | A later commit will make use of this. Reviewed-by: Dave Airlie <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* anv: Trivially implement multiDrawIndirectJason Ekstrand2017-05-032-24/+34
| | | | Reviewed-by: Iago Toral Quiroga <[email protected]>
* anv: Enable VK_KHX_multiview and SPV_KHR_multiviewJason Ekstrand2017-05-032-0/+5
| | | | Reviewed-by: Iago Toral Quiroga <[email protected]>
* anv/cmd_buffer: Emit instanced draws for multiple viewsJason Ekstrand2017-05-033-5/+135
| | | | Reviewed-by: Iago Toral Quiroga <[email protected]>
* anv/cmd_buffer: Pull indirect draw parameter loading into a helperJason Ekstrand2017-05-031-10/+24
| | | | Reviewed-by: Iago Toral Quiroga <[email protected]>
* anv/pipeline: Add shader lowering for multiviewJason Ekstrand2017-05-034-0/+244
| | | | | | | | v2 (Jason Ekstrand): - Take a view_mask rather than a whole subpass - Build the view mask into the VS shader key Reviewed-by: Iago Toral Quiroga <[email protected]>
* anv/pipeline: Add a subpass field to anv_pipelineJason Ekstrand2017-05-032-5/+8
| | | | | | This simplifies the code a variety of places. Reviewed-by: Iago Toral Quiroga <[email protected]>
* anv/pipeline: Call nir_gather_info laterJason Ekstrand2017-05-031-2/+2
| | | | | | | We want to insert more lowering code that may insert system values and we need to gather info after that lowering. Reviewed-by: Iago Toral Quiroga <[email protected]>
* anv: Move shader hashing to anv_pipelineJason Ekstrand2017-05-033-45/+46
| | | | | | | | | | Shader hashing is very closely related to shader compilation. Putting them right next to each other in anv_pipeline makes it easier to verify that we're actually hashing everything we need to be hashing. The only real change (other than the order of hashing) is that we now hash in the shader stage. Reviewed-by: Iago Toral Quiroga <[email protected]>
* anv/pass: Store the per-subpass view maskJason Ekstrand2017-05-032-0/+21
| | | | Reviewed-by: Iago Toral Quiroga <[email protected]>
* anv: Add the KHX_multiview boilerplateJason Ekstrand2017-05-032-0/+18
| | | | Reviewed-by: Iago Toral Quiroga <[email protected]>
* anv/nir: Delete the apply_dynamic_offsets prototypeJason Ekstrand2017-05-031-3/+0
| | | | | | | | That pass hasn't existed since dd4db84640bbb694f180dd50850c3388f67228be but the prototype stuck around for no reason. Reviewed-by: Elie Tournier <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]>
* spirv: Add support for SPV_KHR_multiviewJason Ekstrand2017-05-033-0/+9
| | | | | Reviewed-by: Iago Toral Quiroga <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* spirv: Bump the SPIR-V header to the latest public versionJason Ekstrand2017-05-031-3/+31
| | | | | Reviewed-by: Iago Toral Quiroga <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* compiler: Add a system value and varying for ViewIndexJason Ekstrand2017-05-035-0/+13
| | | | | Reviewed-by: Iago Toral Quiroga <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* mesa/vbo: reduce prim array sizeBartosz Tomczyk2017-05-031-37/+37
| | | | | | | | | We always use only single element. v2: Change single element arrays to variables Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* mesa: add const qualifier on _mesa_valid_to_render()Brian Paul2017-05-032-2/+2
| | | | Reviewed-by: Marek Olšák <[email protected]>
* i965/vec4: don't modify regioning parameters to the sources of DF align1 ↵Samuel Iglesias Gonsálvez2017-05-031-8/+1
| | | | | | | | | | | | | instructions The regioning parameters are now properly set by convert_to_hw_regs() and we don't need to fix them in the generator. That latter fix previously done in the generator was strictly speaking wrong for any non-identity regions. Signed-off-by: Samuel Iglesias Gonsálvez <[email protected]> Cc: "17.1" <[email protected]> Reviewed-by: Francisco Jerez <[email protected]>
* i965/vec4: fix register width for DF VGRF and UNIFORMSamuel Iglesias Gonsálvez2017-05-031-5/+7
| | | | | | | | | | | | | | | | | | | | | | | On gen7, the swizzles used in DF align16 instructions works for element size of 32 bits, so we can address only 2 consecutive DFs. As we assumed that in the rest of the code and prepare the instructions for this (scalarize_df()), we need to set it to two again. However, for DF align1 instructions, a width of 2 is wrong as we are not reading the data we want. For example, an uniform would have a region of <0, 2, 1> so it would repeat the first 2 DFs, when we wanted to access to the first 4. This patch sets the default one to 4 and then modifies the width of align16 instruction's DF sources when we translate the logical swizzle to the physical one. v2: - Remove conditional (Curro). Signed-off-by: Samuel Iglesias Gonsálvez <[email protected]> Cc: "17.1" <[email protected]> Reviewed-by: Francisco Jerez <[email protected]>
* i965/vec4: fix vertical stride to avoid breaking region parameter ruleSamuel Iglesias Gonsálvez2017-05-031-18/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | From IVB PRM, vol4, part3, "General Restrictions on Regioning Parameters": "If ExecSize = Width and HorzStride ≠ 0, VertStride must be set to Width * HorzStride." In next patch, we are going to modify the region parameter for uniforms and vgrf. For uniforms that are the source of DF align1 instructions, they will have <0, 4, 1> regioning and the execsize for those instructions will be 4, so they will break the regioning rule. This will be the same for VGRF sources where we use the vstride == 0 exploit. As we know we are not going to cross the GRF boundary with that execsize and parameters (not even with the exploit), we just fix the vstride here. v2: - Move is_align1_df() (Curro) - Refactor exec_size == width calculation (Curro) Signed-off-by: Samuel Iglesias Gonsálvez <[email protected]> Cc: "17.1" <[email protected]> Reviewed-by: Francisco Jerez <[email protected]>
* radv/ac: canonicalize the output for 32-bit float min/max.Dave Airlie2017-05-031-0/+8
| | | | | | | | | | | | | | | | | | This fixes: dEQP-VK.glsl.builtin.precision.min.* dEQP-VK.glsl.builtin.precision.max.* dEQP-VK.glsl.builtin.precision.clamp.* The problem is the hw doesn't compare denorms properly, so we have to flush them, even though the spec says flushing is optional, if you don't flush the results should be correct. The -pro driver changes the shader float mode, it would be nice if llvm could grow that perhaps. Acked-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: flush f32->f16 conversion denormals to zero. (v2)Dave Airlie2017-05-032-4/+41
| | | | | | | | | | | | | | | SPIR-V defines the f32->f16 operation as flushing denormals to 0, this compares the class using amd class opcode. Thanks to Matt Arsenault for figuring it out. This fix is VI+ only, add a TODO for SI/CIK. This fixes: dEQP-VK.spirv_assembly.instruction.compute.opquantize.flush_to_zero Acked-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: Add userspace fence buffer per context.Bas Nieuwenhuizen2017-05-034-37/+44
| | | | | | | | | | Having it in the winsys didn't work when multiple devices use the same winsys, as we then have multiple contexts per queue, and each context counts separately. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]> Fixes: 7b9963a28f4 "radv: Enable userspace fence checking."
* radv: enable lower_sub to fix loop unrolling.Dave Airlie2017-05-031-0/+1
| | | | | | | | | | Loop unroll asserts if it hits a sub, we don't really want to lower subs as llvm handles these things, but do this for now, until we can fix loop unroll to work with subs. Fixes: 14ae0bfa5 (radv: Add NIR loop unrolling) Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: Don't set dynamic state for pipelines with rasterizer dicard.Bas Nieuwenhuizen2017-05-031-6/+9
| | | | | | | | | | | | All of the dynamic states apply to rasterization & fragment processing, so we don't need to set them if we don't rasterize. We don't clear the dirty flags for them though, so we don't miss any updates for the next pipeline with rasterization. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]> Fixes: 76603aa90b8 "radv: Drop the default viewport when 0 viewports are given."
* radv: flush more stages when semaphore are waiting.Dave Airlie2017-05-032-3/+23
| | | | | | | | | | | | | | | This still doesn't give us complete pWaitDstStageMask support, but it should provide enough to be correct if not as efficent as possible. If we have wait semaphores we must flush between submits and flush the shaders as well. This fixes the remaining fails in: dEQP-VK.synchronization.op.single_queue.semaphore.*ssbo* Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* glsl: set vector_elements to 1 for samplersSamuel Pitoiset2017-05-022-16/+6
| | | | | | | | | | | | | | | | I don't see any reasons why vector_elements is 1 for images and 0 for samplers. This increases consistency and allows to clean up some code a bit. This will also help for ARB_bindless_texture. No piglit regressions with RadeonSI. This time the Intel CI system doesn't report any failures. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Timothy Arceri <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* vc4: Use runtime CPU detection for whether NEON is available.Eric Anholt2017-05-022-14/+16
| | | | | | | | This will allow Raspbian's ARMv6 builds to take advantage of the new NEON code, and could prevent problems if vc4 ends up getting used on a v7 CPU without NEON. v2: Drop dead NEON_SUFFIX (noted by Erik Faye-Lund)
* vc4: Use a wrapper file to set VC4_BUILD_NEON instead of CFLAGS.Eric Anholt2017-05-024-8/+31
| | | | | | | | | Android.mk was setting the flag across the entire driver, so we didn't have non-NEON versions getting built. This was going to be a problem with the next commit, when I start auto-detecting NEON support and use the non-NEON version when appropriate. Reviewed-by: Rob Herring <[email protected]>
* gallium: Enable ARM NEON CPU detection.Eric Anholt2017-05-023-0/+46
| | | | | | | | | | | | | | | | | | I wrote this code with reference to pixman, though I've only decided to cover Linux (what I'm testing) and Android (seems obvious enough). Linux has getauxval() as a cleaner interface to the /proc entry, but it's more glibc-specific and I didn't want to add detection for that. This will be used to enable NEON at runtime on ARMv6 builds of vc4. v2: Actually initialize the temp vars in the Android path (noticed by daniels) v3: Actually pull in the cpufeatures library (change by robher). Use O_CLOEXEC. Break out of the loop when we find our feature. v4: Drop VFP code, which was confused about what it was detecting and not actually used yet. Reviewed-by: Grazvydas Ignotas <[email protected]>
* radv: fix stencil only clears.Dave Airlie2017-05-031-0/+3
| | | | | | | | | | | | | | | If we are clearing stencil only, we still need to provide a a valid Z output from the vertex shader, we can't rely on the depth clear value having any meaning, as we use this for the position output, and it could get clipped, so we don't end up clearing anything. Fixes: dEQP-VK.renderpass.simple.stencil since I added S8 support. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
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