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* winsys/radeon: move variables from radeon_bomgr to radeon_drm_winsysMarek Olšák2015-12-113-126/+129
| | | | | | | | radeon_bomgr is going away. Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Edward O'Callaghan <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* winsys/radeon: remove redundant radeon_bomgr::vaMarek Olšák2015-12-111-7/+4
| | | | | | Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Edward O'Callaghan <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* winsys/amdgpu: don't use the "rws" abbreviation for amdgpu_winsysMarek Olšák2015-12-114-20/+20
| | | | | | Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Edward O'Callaghan <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* winsys/amdgpu: use pb_cache instead of pb_cache_managerMarek Olšák2015-12-114-173/+78
| | | | | | | | This is a prerequisite for the removal of radeon_winsys_cs_handle. Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Edward O'Callaghan <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* gallium/pb_bufmgr_cache: use the new pb_cache moduleMarek Olšák2015-12-111-198/+34
| | | | | | Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Edward O'Callaghan <[email protected]> Acked-by: Michel Dänzer <[email protected]>
* gallium/pb_cache: add a copy of cache bufmgr independent of pb_managerMarek Olšák2015-12-113-0/+362
| | | | | | | | | | | | | | | This simplified (basically duplicated) version of pb_cache_manager will allow removing some ugly hacks from radeon and amdgpu winsyses and flatten simplify their design. The difference is that winsyses must manually add buffers to the cache in "destroy" functions and the cache doesn't know about the buffers before that. The integration is therefore trivial and the impact on the winsys design is negligible. Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Edward O'Callaghan <[email protected]> Acked-by: Michel Dänzer <[email protected]>
* radeonsi: implement fast stencil clearMarek Olšák2015-12-114-23/+53
| | | | Reviewed-by: Alex Deucher <[email protected]>
* radeonsi: re-enable Hyper-Z for stencilMarek Olšák2015-12-111-9/+3
| | | | Reviewed-by: Alex Deucher <[email protected]>
* r600g: remove a Hyper-Z workaround that's likely not needed anymoreMarek Olšák2015-12-111-19/+7
| | | | | | FORCE_OFF == 0, no need to set that Reviewed-by: Alex Deucher <[email protected]>
* r600g: re-enable Hyper-Z for stencil on Evergreen & CaymanMarek Olšák2015-12-111-4/+1
| | | | Reviewed-by: Alex Deucher <[email protected]>
* gallium/radeon: fix Hyper-Z hangs by programming PA_SC_MODE_CNTL_1 correctlyMarek Olšák2015-12-113-5/+18
| | | | | | | | | | This is the recommended setting according to hw people and it makes Hyper-Z stable. Just the two magic states. This fixes Evergreen, Cayman, SI, CI, VI (using the Cayman code). Cc: 11.0 11.1 <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* radeonsi: don't use the CP DMA workaround on Fiji and newerMarek Olšák2015-12-111-16/+20
| | | | Reviewed-by: Alex Deucher <[email protected]>
* radeonsi: apply the streamout workaround to Fiji as wellMarek Olšák2015-12-111-1/+3
| | | | | Cc: 11.0 11.1 <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* radeonsi: also print hexadecimal values for register fields in the IB parserMarek Olšák2015-12-111-4/+7
| | | | | Reviewed-by: Michel Dänzer <[email protected] Reviewed-by: Edward O'Callaghan <[email protected]>
* radeonsi: implement RB+ for Stoney (v2)Marek Olšák2015-12-115-2/+170
| | | | | | v2: fix dual source blending Reviewed-by: Alex Deucher <[email protected]>
* radeonsi: don't call of u_prims_for_vertices for patches and rectanglesMarek Olšák2015-12-111-1/+13
| | | | | | | | | Both caused a crash due to a division by zero in that function. This is an alternative fix. Cc: 11.0 11.1 <[email protected]> Reviewed-by: Michel Dänzer <[email protected]> Reviewed-by: Edward O'Callaghan <[email protected]>
* radeonsi: use tgsi_shader_info::colors_writtenMarek Olšák2015-12-113-11/+1
| | | | Reviewed-by: Alex Deucher <[email protected]>
* r600g: write all MRTs only if there is exactly one output (fixes a hang)Marek Olšák2015-12-111-1/+2
| | | | | | | | This fixes a hang in piglit/arb_blend_func_extended-fbo-extended-blend-pattern_gles2 on REDWOOD. Cc: 11.0 11.1 <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* tgsi/scan: add flag colors_writtenMarek Olšák2015-12-112-0/+4
| | | | | | | This is a prerequisite for the following r600g fix. Cc: 11.0 11.1 <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* Revert "radeonsi: disable DCC on Stoney"Marek Olšák2015-12-111-4/+0
| | | | | | | | | | | This reverts commit 32f05fadbbdf2a3fb60055e610bbbdcd82dd3ce5. It turned out the problem with Stoney was caused by incorrect handling of a non-power-two VRAM size in the kernel driver. This is an optional BIOS setting and can be worked around by choosing a different VRAM size in the BIOS. Cc: 11.1 <[email protected]>
* nir: silence uninitialized warningTimothy Arceri2015-12-111-1/+1
| | | | Reviewed-by: Rob Clark <[email protected]>
* mesa/shader: return correct attribute location for double matrix arraysDave Airlie2015-12-111-3/+8
| | | | | | | | | | | | | | | | | | | If we have a dmat2[4], then dmat2[0] is at 17, dmat2[1] at 19, dmat2[2] at 21 etc. The old code was returning 17,18,19. I think this code is also wrong for float matricies as well. There is now a piglit for the float case. This partly fixes: GL41-CTS.vertex_attrib_64bit.limits_test [airlied: update with Tapani suggestion to clean it up]. Cc: "11.0 11.1" <[email protected]> Reviewed-by: Timothy Arceri <[email protected]> Reviewed-by: Tapani Pälli <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* draw: fix clipping with linear interpolated values and gl_ClipVertexRoland Scheidegger2015-12-111-4/+4
| | | | | | | | | | | | | | | | Discovered this when working on other clip code, apparently didn't work correctly - the combination of linear interpolated values and using gl_ClipVertex produced wrong values (failing all such combinations in piglits glsl-1.30 interpolation tests, named interpolation-noperspective-XXX-vertex). Use the pre-clip-pos values when determining the interpolation factor to fix this. Noone really understands this code well, but everybody agrees this looks sane... This fixes all those failing tests (10 in total) both with the llvm and non-llvm draw paths, with no piglit regressions. Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* r600: add missing return value check.Dave Airlie2015-12-111-0/+2
| | | | | | Pointed out by coverity scan. Signed-off-by: Dave Airlie <[email protected]>
* nir: Get rid of *_indirect variants of input/output load/store intrinsicsJason Ekstrand2015-12-1019-414/+391
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is some special-casing needed in a competent back-end. However, they can do their special-casing easily enough based on whether or not the offset is a constant. In the mean time, having the *_indirect variants adds special cases a number of places where they don't need to be and, in general, only complicates things. To complicate matters, NIR had no way to convdert an indirect load/store to a direct one in the case that the indirect was a constant so we would still not really get what the back-ends wanted. The best solution seems to be to get rid of the *_indirect variants entirely. This commit is a bunch of different changes squashed together: - nir: Get rid of *_indirect variants of input/output load/store intrinsics - nir/glsl: Stop handling UBO/SSBO load/stores differently depending on indirect - nir/lower_io: Get rid of load/store_foo_indirect - i965/fs: Get rid of load/store_foo_indirect - i965/vec4: Get rid of load/store_foo_indirect - tgsi_to_nir: Get rid of load/store_foo_indirect - ir3/nir: Use the new unified io intrinsics - vc4: Do all uniform loads with byte offsets - vc4/nir: Use the new unified io intrinsics - vc4: Fix load_user_clip_plane crash - vc4: add missing src for store outputs - vc4: Fix state uniforms - nir/lower_clip: Update to the new load/store intrinsics - nir/lower_two_sided_color: Update to the new load intrinsic NIR and i965 changes are Reviewed-by: Kenneth Graunke <[email protected]> NIR indirect declarations and vc4 changes are Reviewed-by: Eric Anholt <[email protected]> ir3 changes are Reviewed-by: Rob Clark <[email protected]> NIR changes are Acked-by: Rob Clark <[email protected]>
* i965/fs_nir: Refactor store_output, load_input, and load_uniformJason Ekstrand2015-12-101-26/+19
| | | | | | | | There was way too much incrementing of things going on. Instead, let's just start everything off at the right base location, and then increment in the loop. Reviewed-by: Kenneth Graunke <[email protected]>
* gallium/util: return correct number of bound vertex buffersPatrick Rudolph2015-12-101-1/+7
| | | | | | | | | | | | | | | | | | | | In case a state tracker unbinds every slot by a seperate pipe->set_vertex_buffers() call, starting from slot zero, the number of bound buffers would not reach zero at all. The current algorithm does not account for pre-existing holes in the buffer list. Unbinding all buffers at once or starting at the top-most slot results in correct behaviour. Calculating the correct number of bound buffers fixes a NULL pointer dereference in nvc0_validate_vertex_buffers_shared(). Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93004 Signed-off-by: Patrick Rudolph <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]> Cc: "11.0 11.1" <[email protected]>
* blit: Don't take into account the Mesa format when checking MSRT blitNeil Roberts2015-12-101-13/+15
| | | | | | | | | | | | | | | | | | | | | | According to the GLES3 spec, blitting between multisample FBOs with different internal formats should not be allowed. The compatible_resolve_formats function implements this check. Previously it had a shortcut where if the Mesa formats of the two renderbuffers were the same then it would assume the blit is ok. However some drivers map different internal formats to the same Mesa format, for example it might implement both GL_RGB and GL_RGBA textures with MESA_FORMAT_R8G8B8A_UNORM. The function is used to generate a GL error according to what the GL spec requires so the blit should not be allowed in that case. This patch just removes the shortcut so that it only ever looks at the internal format. Note that I posted a related patch to disable this check altogether for desktop GL. However this function is still used on GLES3 because there are conformance tests that require this behaviour so this patch is still useful. Cc: Marek Olšák <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* i965: Check base format to determine whether to use tiled memcpyNeil Roberts2015-12-102-6/+8
| | | | | | | | | | | | | The tiled memcpy doesn't work for copying from RGBX to RGBA because it doesn't override the alpha component to 1.0. Commit 2cebaac479d4 added a check to disable it for RGBX formats by looking at the TexFormat. However a lot of the rest of the code base is written with the assumption that an RGBA texture can be used internally to implement a GL_RGB texture. If that is done then this check breaks. This patch makes it instead check the base format of the texture which I think more directly matches the intention. Reviewed-by: Jason Ekstrand <[email protected]>
* i965/gen8: Allow rendering to B8G8R8X8Neil Roberts2015-12-101-4/+5
| | | | | | | | | Since Gen8 this is allowed as a rendering target so we don't need to override it to B8G8R8A8. This is helpful on Gen9+ where using this override causes fast clears not to work. Reviewed-by: Anuj Phogat <[email protected]> Reviewed-by: Ben Widawsky <[email protected]>
* i965/gen9: Allow fast clear for MSRT formats matching renderNeil Roberts2015-12-101-4/+11
| | | | | | | | | | | | | | | | | Previously fast clear was disallowed on Gen9 for MSRTs with the claim that some formats don't work but we didn't understand why. On further investigation it seems the formats that don't work are the ones where the render surface format is being overriden to a different format than the one used for texturing. The one used for texturing is not actually a renderable format. It arguably makes sense that the sampler hardware doesn't handle the fast color correctly in these cases because it shouldn't be possible to end up with a fast cleared surface that is non-renderable. This patch changes the limitation to prevent fast clear for surfaces where the format for rendering is overriden. Reviewed-by: Ben Widawsky <[email protected]>
* i965/gen9/fast-clear: Handle linear→SRGB conversionNeil Roberts2015-12-101-0/+11
| | | | | | | | | | | | | | | If GL_FRAMEBUFFER_SRGB is enabled when writing to an SRGB-capable framebuffer then the color will be converted from linear to SRGB before being written. There is no chance for the hardware to do this itself because it can't modify the clear color that is programmed in the surface state so it seems pretty clear that the driver should be handling this itself. Note that this wasn't a problem before Gen9 because previously we were only able to do fast clears to 0 or 1 and those values are the same in linear and SRGB space. Reviewed-by: Topi Pohjolainen <[email protected]>
* docs: Add ARB_compute_shader to 11.2.0 release notesJordan Justen2015-12-091-0/+1
| | | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* docs: Mark ARB_compute_shader as done for i965Jordan Justen2015-12-091-2/+2
| | | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965: Enable ARB_compute_shader extension on supported hardwareJordan Justen2015-12-092-5/+8
| | | | | | | | | | | | | | | Enable ARB_compute_shader on gen7+, on hardware that supports the OpenGL 4.3 requirements of a local group size of 1024. With SIMD16 support, this is limited to Ivy Bridge and Haswell. Broadwell will work with a local group size up to 896 on SIMD16 meaning programs that use this size or lower should run when setting MESA_EXTENSION_OVERRIDE=GL_ARB_compute_shader. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965/nir: Implement shared variable atomic operationsJordan Justen2015-12-092-0/+60
| | | | | | | | | v3: * Update based on latest SSBO code (Iago) Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* nir: Add nir intrinsics for shared variable atomic operationsJordan Justen2015-12-092-0/+94
| | | | | | | | | v3: * Update min/max based on latest SSBO code (Iago) Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* glsl: Disable several optimizations on shared variablesJordan Justen2015-12-093-3/+6
| | | | | | | | | | Shared variables can be accessed by other threads within the same local workgroup. This prevents us from performing certain optimizations with shared variables. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* glsl: Buffer atomics are supported for compute shadersJordan Justen2015-12-091-32/+38
| | | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* glsl: Translate atomic intrinsic functions on shared variablesJordan Justen2015-12-091-0/+148
| | | | | | | | | | | | | | | | | When an intrinsic atomic operation is used on a shared variable, we translate it to a new 'shared variable' specific intrinsic function call. For example, a call to __intrinsic_atomic_add when used on a shared variable will be translated to a call to __intrinsic_atomic_add_shared. v3: * Fix stale comments copied from SSBOs (Iago) Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* glsl: Check for SSBO variable in check_for_ssbo_storeJordan Justen2015-12-091-1/+1
| | | | | | | | | The compiler probably already blocks this earlier on, but we should be checking for an SSBO here. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* glsl: Check for SSBO variable in SSBO atomic loweringJordan Justen2015-12-091-0/+14
| | | | | | | | | | | | | When an atomic function is called, we need to check to see if it is for an SSBO variable before lowering it to the SSBO specific intrinsic function. v2: * is_in_buffer_block => is_in_shader_storage_block (Iago) Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* glsl: Replace atomic_ssbo and ssbo_atomic with atomicJordan Justen2015-12-093-132/+132
| | | | | | | | | | | | | | | | | The atomic functions can also be used with shared variables in compute shaders. When lowering the intrinsic in lower_ubo_reference, we still create an SSBO specific intrinsic since SSBO accesses can be indirectly addressed, whereas all compute shader shared variable live in a single shared variable area. v2: * Also remove the _internal suffix from ssbo atomic intrinsic names (Iago) Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* glsl: Allow atomic functions to be used with shared variablesJordan Justen2015-12-091-8/+10
| | | | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Timothy Arceri <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965: Lower shared variable references to intrinsic callsJordan Justen2015-12-091-0/+3
| | | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965: Enable shared local memory for CS shared variablesJordan Justen2015-12-093-0/+27
| | | | | | | | | v3: * Check shared variable size at link time Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965/fs: Handle nir shared variable store intrinsicJordan Justen2015-12-091-0/+48
| | | | | | | | | | | | v4: * Apply similar optimization for shared variable stores as 0cb7d7b4b7c32246d4c4225a1d17d7ff79a7526d. This was causing a OpenGLES 3.1 CTS failure, but 867c436ca841b4196b4dde4786f5086c76b20dd7 fixes that. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965/fs: Handle nir shared variable load intrinsicJordan Justen2015-12-091-0/+28
| | | | | | | | | | v3: * Remove extra #includes (Iago) * Use recently added GEN7_BTI_SLM instead of BRW_SLM_SURFACE_INDEX (curro) Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965: Disable vector splitting on shared variablesJordan Justen2015-12-091-0/+1
| | | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* nir: Translate glsl shared var store intrinsic to nir intrinsicJordan Justen2015-12-092-1/+35
| | | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
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