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* gallium/drivers/nouveau: Make use of ARRAY_SIZE macroEdward O'Callaghan2015-12-0614-22/+20
| | | | | Signed-off-by: Edward O'Callaghan <[email protected]> Signed-off-by: Marek Olšák <[email protected]>
* gallium/radeon*: Remove useless castsEdward O'Callaghan2015-12-065-14/+11
| | | | | | | | These are unnecessary and are likely just left overs from prior work. Signed-off-by: Edward O'Callaghan <[email protected]> Signed-off-by: Marek Olšák <[email protected]>
* nv50/ir: fold shl + mul with immediatesIlia Mirkin2015-12-051-0/+16
| | | | | | | | | | | | | | On SM20 this gives: total instructions in shared programs : 6299222 -> 6294240 (-0.08%) total gprs used in shared programs : 944139 -> 944068 (-0.01%) total local used in shared programs : 54116 -> 54116 (0.00%) local gpr inst bytes helped 0 126 2781 2781 hurt 0 55 11 11 Signed-off-by: Ilia Mirkin <[email protected]>
* nv50/ir: propagate indirect loads into instructionsIlia Mirkin2015-12-051-0/+52
| | | | | | | | | | | | | | | | This way $r1 = $r0 + 4; c1[$r1] becomes c1[$r0+4]. On SM35: total instructions in shared programs : 6206257 -> 6185058 (-0.34%) total gprs used in shared programs : 911045 -> 910722 (-0.04%) total local used in shared programs : 39072 -> 39072 (0.00%) local gpr inst bytes helped 0 417 4195 4195 hurt 0 280 0 0 Signed-off-by: Ilia Mirkin <[email protected]>
* nv50/ir: flip shl(add, imm) into add(shl, imm)Ilia Mirkin2015-12-051-4/+34
| | | | | | | | | | | | | | | | | This works when the add also has an immediate. This often happens in address calculations. These addresses can then be inlined as well. On code targeted to SM35: total instructions in shared programs : 6223346 -> 6206257 (-0.27%) total gprs used in shared programs : 911075 -> 911045 (-0.00%) total local used in shared programs : 39072 -> 39072 (0.00%) local gpr inst bytes helped 0 119 3664 3664 hurt 0 74 15 15 Signed-off-by: Ilia Mirkin <[email protected]>
* vc4: Fix accidental scissoring when scissor is disabled.Eric Anholt2015-12-051-5/+23
| | | | | | | | Even if the rasterizer has scissor disabled, we'll have whatever vc4->scissor bounds were last set when someone set up a scissor, so we shouldn't clip to them in that case. Fixes piglit fbo-blit-rect, and a lot of MSAA tests once they're enabled.
* vc4: Disable RCL blitting when scissors are enabled.Eric Anholt2015-12-051-0/+3
| | | | | | | | We could potentially handle scissored blits when they're tile aligned, but it doesn't seem worth it. If you're doing a scissored blit, you're probably a testcase. Fixes piglit's fbo-scissor-blit fbo
* vc4: Bring over cleanups from submitting to the kernel.Eric Anholt2015-12-054-87/+78
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* nvc0: expose a group of performance metrics for SM30 (Kepler)Samuel Pitoiset2015-12-052-2/+8
| | | | | | | This allows to monitor these performance metrics through GL_AMD_performance_monitor. Signed-off-by: Samuel Pitoiset <[email protected]>
* nvc0: re-introduce performance metrics for SM30 (Kepler)Samuel Pitoiset2015-12-052-5/+188
| | | | | | | This implements more performance metrics than the previous support, but some other metrics still need to be figured out. Signed-off-by: Samuel Pitoiset <[email protected]>
* nvc0: remove useless counting operations for MP countersSamuel Pitoiset2015-12-051-101/+5
| | | | | | Those bits were related to old performance metrics support. Signed-off-by: Samuel Pitoiset <[email protected]>
* nvc0: remove old performance metrics support on KeplerSamuel Pitoiset2015-12-052-37/+0
| | | | | | | These performance metrics will be re-introduced in an upcoming patch that will follow the same design as Fermi. Signed-off-by: Samuel Pitoiset <[email protected]>
* nvc0: remove wrong inst_issued HW SM perf counter on KeplerSamuel Pitoiset2015-12-052-3/+0
| | | | | | | inst_issued is performance metric not a hardware event on Kepler (SM30). It will be re-introduced in an upcoming patch. Signed-off-by: Samuel Pitoiset <[email protected]>
* nvc0: add missing HW SM perf counters for SM30 (Kepler)Samuel Pitoiset2015-12-053-0/+10
| | | | | | | SM30 is the compute capability version for GK104/GK106/GK107. This also introduces a new signal group selection called UNK0F. Signed-off-by: Samuel Pitoiset <[email protected]>
* nvc0: fix the comment that describe MP counters storage on KeplerSamuel Pitoiset2015-12-051-0/+5
| | | | Signed-off-by: Samuel Pitoiset <[email protected]>
* freedreno/ir3: nir shader prints with 'disasm' debug optionRob Clark2015-12-051-2/+2
| | | | | | | | Move these to 'disasm' instead of the more verbose 'optmsgs' since, like the tgsi dumps, it is useful without the more verbose compiler logging enabled. Signed-off-by: Rob Clark <[email protected]>
* gallium/util: fix pipe_debug_message macro to allow 0 argsIlia Mirkin2015-12-041-1/+1
| | | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Brian Paul <[email protected]> Tested-by: Brian Paul <[email protected]>
* vc4: Add debug dumping of MSAA surfaces.Eric Anholt2015-12-042-6/+145
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* vc4: Add support for laying out MSAA resources.Eric Anholt2015-12-041-5/+20
| | | | | | For MSAA, we store full resolution tile buffer contents, which have their own tiling format. Since they're full resolution buffers, we have to align their size to full tiles.
* vc4: Add support for storing sample mask.Eric Anholt2015-12-045-0/+24
| | | | | From the API perspective, writing 1 bits can't turn on pixels that were off, so we AND it with the sample mask from the payload.
* vc4: Fix up tile alignment checks for blitting using just an RCL.Eric Anholt2015-12-041-6/+22
| | | | | | | | We were checking that the blit started at 0 and was 1:1, but not that it went to the full width of the surface, or that the width was aligned to a tile. We then told it to blit to the full width/height of the surface, causing contents to be stomped in a bunch of MSAA tests that happen to include half-screen-width blits to 0,0.
* vc4: Add support for loading sample mask.Eric Anholt2015-12-046-1/+19
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* freedreno/ir3: convert scheduler back to recursive algoRob Clark2015-12-042-127/+204
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | I've played with a few different approaches to tweak instruction priority according to how much they increase/decrease register pressure, etc. But nothing seems to change the fact that compared to original (pre-multiple-block-support) scheduler, in some edge cases we are generating shaders w/ 5-6x higher register usage. The problem is that the priority queue approach completely looses the dependency between instructions, and ends up scheduling all paths at the same time. Original reason for switching was that recursive approach relied on starting from the shader outputs array. But we can achieve more or less the same thing by starting from the depth-sorted list. shader-db results: total instructions in shared programs: 113350 -> 105183 (-7.21%) total dwords in shared programs: 219328 -> 211168 (-3.72%) total full registers used in shared programs: 7911 -> 7383 (-6.67%) total half registers used in shader programs: 109 -> 109 (0.00%) total const registers used in shared programs: 21294 -> 21294 (0.00%) half full const instr dwords helped 0 322 0 711 215 hurt 0 163 0 38 4 The shaders hurt tend to gain a register or two. While there are also a lot of helped shaders that only loose a register or two, the more complex ones tend to loose significanly more registers used. In some more extreme cases, like glsl-fs-convolution-1.shader_test it is more like 7 vs 34 registers! Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: don't reuse a0.x across blocksRob Clark2015-12-041-7/+14
| | | | | | | | It causes confusion in sched if we need to split_addr() since otherwise we wouldn't easily know which block the new addr instr will be scheduled in. So just side-step the whole situation. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: rename ir3_block::bdRob Clark2015-12-043-11/+11
| | | | | | | | We'll need to add similar for ir3_instruction, but following the pattern to use 'id' seems confusing. Let's just go w/ generic 'data' as the name. Signed-off-by: Rob Clark <[email protected]>
* util: fix comment typoGiuseppe Bilotta2015-12-041-1/+1
| | | | | | | | Undefining the NDEBUG is relevant for release build, as they are the ones that set it. [Emil Velikov: split from previous patch] Signed-off-by: Emil Velikov <[email protected]>
* xvmc: force assertion in XvMC testsGiuseppe Bilotta2015-12-045-0/+10
| | | | | | | | | | | | | | | This follows the src/util/u_atomic_test.c model of undefining NDEBUG unconditionally throughouth the XvMC tests, to force asserts regardless of debug mode. The comment on u_atomic_test.c is also fixed (read 'debug' where it should have been 'release'). v2: s/debug/release/ in relevant comments Signed-off-by: Giuseppe Bilotta <[email protected]> [Emil Velikov: keep the src/util/ hunk as separate patch] Signed-off-by: Emil Velikov <[email protected]>
* radeon: const correctnessGiuseppe Bilotta2015-12-041-1/+1
| | | | | | | | Add missing `const` specifier for pointer pointing to a const struct. Signed-off-by: Giuseppe Bilotta <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* radeon: whitespace cleanupGiuseppe Bilotta2015-12-041-2/+2
| | | | | | Signed-off-by: Giuseppe Bilotta <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* mesa/tests: add KHR_debug GLES glGetPointervKHR entry pointsEmil Velikov2015-12-041-1/+4
| | | | | | | | | | | | | | Should have been part of commit f53f9eb8d49 "glapi: add GetPointervKHR to the ES dispatch". v2: comment out the ES1.1 symbol and use the same description (pattern) as elsewhere (Matt) Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93235 Fixes: f53f9eb8d49 "glapi: add GetPointervKHR to the ES dispatch". Signed-off-by: Emil Velikov <[email protected]> Tested-by: Vinson Lee <[email protected]> (v1) Tested-by: Michel Dänzer <[email protected]>
* i965/vec4: Stop pretending to support indirect output storesJason Ekstrand2015-12-031-9/+3
| | | | | | | | | | | Since we're using nir_lower_outputs_to_temporaries to shadow all our outputs, it's impossible to actually get an indirect store. The code we had to "handle" this was pretty bogus as it created a register with a reladdr and then stuffed it in a fixed varying slot without so much as a MOV. Not only does this not do the MOV, it also puts the indirect on the wrong side of the transaction. Let's just delete the broken dead code. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/vec4: Get rid of the nir_inputs arrayJason Ekstrand2015-12-033-40/+13
| | | | | | | | It's not really buying us anything at this point. It's just a way of remapping one offset namespace onto another. We can just use the location namespace the whole way through. Reviewed-by: Kenneth Graunke <[email protected]>
* nir/lower_io: Pass the builder and type_size into get_io_offsetJason Ekstrand2015-12-031-15/+15
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* nv50/ir: replace zeros in movs as wellIlia Mirkin2015-12-031-2/+1
| | | | | | | | | The original change to put zeroes directly into instructions created conditional mov's with the zero immediate. However that can't be emitted, so make sure to replace the zero with r63. Fixes: 52a800a68 (nv50/ir: allow immediate 0 to be loaded anywhere) Signed-off-by: Ilia Mirkin <[email protected]>
* nv50/ir: fold fma/mad when all 3 args are immediatesIlia Mirkin2015-12-031-0/+30
| | | | | | This happens pretty rarely, but might as well do it when it does. Signed-off-by: Ilia Mirkin <[email protected]>
* nv50/ir: avoid looking at uninitialized srcMods entriesIlia Mirkin2015-12-032-2/+2
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Cc: "11.0 11.1" <[email protected]>
* nv50/ir: fix DCE to not generate 96-bit loadsIlia Mirkin2015-12-031-1/+31
| | | | | | | | | | A situation where there's a 128-bit load where the last component gets DCE'd causes a 96-bit load to be generated, which no GPU can actually emit. Avoid generating such instructions by scaling back to 64-bit on the first load when splitting. Signed-off-by: Ilia Mirkin <[email protected]> Cc: "11.0 11.1" <[email protected]>
* draw: fix clipping of layer/vp index outputsRoland Scheidegger2015-12-041-139/+186
| | | | | | | | | | | | | | | | | | | | | This was just plain broken. It used always the value from v0 (for vp_index) but would pass the value from the provoking vertex to later stages - but only if there was a corresponding fs input, otherwise the layer/vp index would get lost completely (as it would try to interpolate the (unsigned) values as floats). So, make it obey provoking vertex rules (drivers relying on draw will need to do the same). And make sure that the default interpolation mode (when no corresponding fs input is found) for them is constant. Also, change the code a bit so constant inputs aren't interpolated then copied over later. Fixes the new piglit test gl-layer-render-clipped. v2: more consistent whitespaces fixes for function defs, and more tab killing (overall still not quite right however). Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Jose Fonseca <[email protected]>
* softpipe: use provoking vertex for layerRoland Scheidegger2015-12-041-2/+2
| | | | | | | | Same as for llvmpipe, albeit softpipe only really handles multiple layers, not multiple viewports/scissors. Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Jose Fonseca <[email protected]>
* llvmpipe: use provoking vertex for layer/viewportRoland Scheidegger2015-12-042-17/+32
| | | | | | | | | | | | | | | | | | | | d3d10 actually requires using provoking (first) vertex. GL is happy with any vertex (as long as we say it's undefined in the corresponding queries). Up to now we actually used vertex 0 for viewport index, and vertex 1 for layer (for tris), which really didn't make sense (probably a typo). Also,$ since we reorder vertices of clockwise triangle, that actually meant we used a different vertex depending if the traingle was cw or ccw (still ok by gl). However, it should be consistent with what draw (clip) does, and using provoking vertex seems like the sensible choice (draw clip will be fixed next as it is totally broken there). While here, also use the correct viewport always even when not needed in setup (we pass it down to jit fragment shader it might be needed there for getting correct near/far depth values). No piglit changes. Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Jose Fonseca <[email protected]>
* vc4: Add the RCL to CL debug dumping when in simulator mode.Eric Anholt2015-12-031-0/+6
| | | | | | We can't dump it in the real driver, since the kernel doesn't give us a handle to it (except after a GPU hang, using a root ioctl). In the simulator we can.
* radeonsi: fix Fiji for LLVM <= 3.7Marek Olšák2015-12-031-1/+2
| | | | | Cc: 11.0 11.1 <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* radeonsi: fix occlusion queries on FijiMarek Olšák2015-12-031-2/+2
| | | | Tested.
* radeonsi: dump init_config IBsMarek Olšák2015-12-031-4/+15
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: print framebuffer info into ddebug logsMarek Olšák2015-12-033-2/+27
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* gallium/radeon: print more info about HTILEMarek Olšák2015-12-032-2/+17
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* gallium/radeon: print more info about CMASKMarek Olšák2015-12-032-3/+16
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* gallium/radeon: rename fmask::pitch -> pitch_in_pixelsMarek Olšák2015-12-033-6/+6
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* gallium/radeon: print more information about texturesMarek Olšák2015-12-031-5/+43
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* gallium/radeon: move printing texture info into a separate functionMarek Olšák2015-12-031-41/+51
| | | | Reviewed-by: Michel Dänzer <[email protected]>
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